Intel PXA26X - Manual (Page 273)

Intel® PXA26x Processor Family Developer’s Manual 7-5
Liquid Crystal Display Controller
• Program all of the LCD configuration registers except the Frame Descriptor Address registers
(FDADRx) and the LCD Controller Configuration Register 0 (LCCR0). See
Section 7.6 for
details of all registers.
• Program FDADRx with the memory address of the palette/frame descriptor, as described in
Section 7.6.5.2 .
• Enable the LCD controller by writing to LCCR0, as described in Section 7.6.1 .
For more information, see Section 7.6.1.14, “LCD Enable (ENB)” .
If the LCD controller is being re-enabled, there has not been a reset since the last programming,
and the GPIO pins are still configured for LCD controller functionality, only the registers FDADRx
and LCCR0 need to be reprogrammed. The LCD Controller Status Register (LCSR) must also be
written to clear any old status flags before re-enabling the LCD controller. See
Section 7.6.7 for
details.
7.2.2 Disabling the Controller
The LCD controller can be disabled in two ways:
• Regular disabling – Recommended method for stopping the LCD controller, is to set the
disable bit (LCCR0[DIS]). Do not change the other bits in LCCR0 — read the register, set the
DIS bit, and rewrite the register. This method causes the LCD controller to stop cleanly at the
end of the current frame being fetched from memory. If the LCD DMAC is fetching palette
data when DIS is set, the palette RAM load is completed, and the next frame is displayed
before the LCD is disabled. The LCD Disable Done bit (LCSR[LDD]) is set when the LCD
controller finishes displaying the last frame fetched, and the enable bit (LCCR0[ENB]) is
cleared automatically by hardware.
• Quick disabling – Accomplished by clearing the enable bit (LCCR0[ENB]). The LCD
controller finishes any current DMA transfer, stops driving the panel, and shuts down
immediately, setting the quick-disable bit (LCSR[QD]). Quick disabling is intended for
situations such as a battery fault, where system bus traffic has to be minimized immediately so
the processor can have enough time to store critical data to memory before the loss of power.
The LCD controller must not be re-enabled until the QD bit is set (equals 1). A set QD bit
indicates that the quick shutdown is complete.
Once disabled, the LCD controller automatically disables its clocks to conserve power. See
Section 7.6.1.5, “LCD Disable (DIS)” for more information.
7.2.3 Resetting the Controller
At reset, the LCD controller is disabled, and the output pins are configured as GPIO pins. All LCD
controller registers are reset to the conditions shown in the register descriptions.
7.3 Detailed Module Descriptions
This section describes the functions of the LCD controller modules:
• Section 7.3.1, “Input FIFOs”
• Section 7.3.2, “Lookup Palette”