Figure 5-7 – Intel PXA26X User Manual
Page 176
5-18
Intel® PXA26x Processor Family Developer’s Manual
Direct Memory Access Controller
Table 5-7. DMA Channel Control/Status Register Bitmap and Bit Definitions (Sheet 1 of 2)
Physical Address
0x4000_0000 - 0x4000_003C
DMA Channel Control/Status
Register (DCSRx)
DMA
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RU
N
NO
DE
SCF
E
T
C
H
STO
P
IRQ
E
N
RESERVED
R
E
Q
PEN
D
RESERVED
ST
O
P
S
T
A
T
E
EN
DIN
T
R
S
T
AR
T
INT
R
BU
SE
R
R
IN
T
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Bits
Name
Description
31
RUN
RUN BIT (read / write):
0 – Stops the channel
1 – Starts the channel
Lets software start or stop the channel. If the run bit is cleared in the middle of the burst, the
burst will complete before the channel is stopped.
Software must write to DDADRx before it sets this bit for Descriptor Fetch Mode.
After the channel stops, the DCSR[STOPSTATE] bit is set to 1. Software must poll the
DCSR[STOPSTATE] bit to determine the channel’s status or set the STOPIRQEN to force
an interrupt after the channel stops. Software must write a 1 to the bit to restart a stopped
channel.
After clearing the run bit to stop the channel, an end interrupt is not guaranteed to happen
if the length bits, DCMDx[LENGTH], is zero. Software must determine if the transfer is
done after clearing the run bit.
30
NODESC
FETCH
NO-DESCRIPTOR FETCH (read / write):
0 – Descriptor Fetch Mode
1 – No-Descriptor Fetch Mode
Determines if the channel has a descriptor.
If this bit is set to a 0, the channel is in Descriptor Fetch Mode. See
“Descriptor Fetch Mode” on page 5-7
for information on the DMAC registers.
If this bit is set to a 1, the channel is in No-Descriptor Fetch Mode. See
“No-Descriptor Fetch Mode” on page 5-6
for information on the DMAC registers.
29
STOPIRQEN
STOP INTERRUPT ENABLE (read / write):
0 – No interrupt if the channel is in uninitialized or stopped state
1 – Enables an interrupt if the channel is in uninitialized or stopped state
Allows an interrupt to pass to the interrupt controller if the DCSR[STOPSTATE] bit is 1. If
the DCSR[STOPINTEN] bit is 0, the interrupt is not generated after the channel stops. If
software writes a 1 to this bit before the channel starts, an interrupt is generated.
28:9
—
Reserved – Read as unknown and must be written as zero.
8
REQPEND
REQUEST PENDING (read-only):
0 – No pending request
1 – The channel has a pending request
Indicates that the DMA channel has a pending request.
7:4
—
Reserved – Read as unknown and must be written as zero.