Intel PXA26X - Manual (Page 244)

6-54 Intel® PXA26x Processor Family Developer’s Manual
Memory Controller
Figure 6-18. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)
(MSC0:RDF = 2, MSC0:RDN = 2, MSC0:RRR = 1)
0 1 2 3
00
0000
tCEH
RRR*2+1 RDF+1+Waits
RDN+1
tASWN
RDF+1+Waits
RDN+1
tAH
tASRW0
tCES
tAS
MEMCLK
nCS[0]
MA[25:2]
MA[1:0]
nOE
nPWE
RDnWR
RDY
MD[31:0]
DQM[3:0]
nCS[1]