Intel PXA26X - Manual (Page 40)

2-10 Intel® PXA26x Processor Family Developer’s Manual
System Architecture
nSDCS[0] OCZ
SDRAM CS FOR BANKS 0 THROUGH 3 (output):
Connect to the chip select (CS) pins for SDRAM. For the
PXA26x processor family nSDCS0 can be Hi-Z, nSDCS1-
3 cannot.
Driven High Driven High
nSDCS[1] OC Driven High Driven High
nSDCS[2]/
GPIO[86]
ICOC
Driven High (but see
Note[8]) Driven High (but
see Note [8])
nSDCS[3]/
GPIO[87]
ICOC
Driven High (but see
Note[8]) Driven High (but
see Note [8])
DQM[3:0] OCZ
SDRAM DQM FOR DATA BYTES 3 THROUGH 0 (output):
Connect to the data output mask enables (DQM) for
SDRAM. Driven Low Driven Low
nSDRAS OCZ
SDRAM RAS (output):
Connect to the row address strobe (RAS) pins for all
banks of SDRAM. Driven High Driven High
nSDCAS OCZ
SDRAM CAS (output):
Connect to the column address strobe (CAS) pins for all
banks of SDRAM. Driven High Driven High
SDCKE[0] OC
Synchronous Static Memory clock enable (output):
Connect to the CKE pins of SMROM. The memory
controller provides control register bits for deassertion. Driven Low Driven Low
SDCKE[1] OC
SDRAM OR SYNCHRONOUS STATIC MEMORY CLOCK
ENABLE (output):
Connect to the clock enable pins of SDRAM. It is
deasserted during sleep. SDCKE[1] is always deasserted
upon reset. The memory controller provides control
register bits for deassertion.
Driven Low Driven Low
SDCLK[0] OC
SYNCHRONOUS STATIC MEMORY CLOCK (output):
Connect to the clock (CLK) pins of SMROM. It is driven by
either the internal memory controller clock, or the internal
memory controller clock divided by 2. At reset, all clock
pins are free running at the divide by 2 clock speed and
may be turned off via free running control register bits in
the memory controller. The memory controller also
provides control register bits for clock division and
deassertion of each SDCLK pin. SDCLK[0] control register
assertion bit defaults to on if the boot-time static memory
bank 0 is configured for SMROM.
SDCLK[1] OCZ
SDRAM CLOCKS (output):
Connect SDCLK[1] and SDCLK[2] to the clock pins of
SDRAM in bank pairs 0/1 and 2/3, respectively. They are
driven by either the internal memory controller clock, or the
internal memory controller clock divided by 2. At reset, all
clock pins are free running at the divide by 2 clock speed
and may be turned off via free running control register bits
in the memory controller. The memory controller also
provides control register bits for clock division and
deassertion of each SDCLK pin. SDCLK[2:1] control
register assertion bits are always deasserted upon reset.
Driven Low Driven Low
SDCLK[2] OC Driven Low Driven Low
Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 2 of 12)
Pin Name Type Signal Descriptions Reset State Sleep State