Intel PXA26X - Manual (Page 234)

6-44 Intel® PXA26x Processor Family Developer’s Manual
Memory Controller
6.8.2 Asynchronous Static Memory Control Registers (MSC0 – 2)
The MSC0, MSC1, and MSC2 are read/write registers and contain control bits for configuring
Static Memory (or Variable Latency I/O) that correspond to chip-select pairs nCS(1:0), nCS(3:2),
and nCS(5:4), respectively. Timing fields are specified as numbers of memory clock cycles. Each
of the three registers contain two identical CNFG fields One for each chip select in the pair.
When programming a different memory type in an MSC register, ensure that the new value has
been accepted and programmed before issuing a command to that memory. To do this, the MSC
register must be read after it is written and before an access to the memory is attempted. This is
especially important when changing from ROM/flash to an unconstrained writable memory type
(such as SRAM).
If any of the nCS[3:0] banks is configured for synchronous static memory via SXCNFG[SXENx],
the corresponding half-words of MSC0 or MSC1 are ignored, except MSCx:RBWx, the data
width. Another exception is non-SDRAM timing synchronous flash, which writes asynchronously
and requires these programmed values. Refer to
Table 6-25 .