Intel PXA26X - Manual (Page 30)

1-6 Intel® PXA26x Processor Family Developer’s Manual
Introduction
1.2.20 Network Synchronous Serial Protocol Port
The PXA26x processor family has an SSP port optimized for connection to other network ASICs.
This NSSP adds a Hi-Z function to TXD, the ability to control when Hi-Z occurs, and swapping the
TXD/RXD pins.
This port is not multiplexed with other interfaces.
1.2.21 Audio Synchronous Serial Protocol Port
The PXA26x processor family has an SSP port optimized for connection to audio ASICs. This
ASSP adds a Hi-Z function to TXD and the ability to control when Hi-Z occurs.
This port is multiplexed on the same pins as the I
2
S port and the AC97 port.
1.2.22 Hardware UART (HWUART)
The PXA26x processor family has a UART with hardware flow control. The HWUART provides a
partial set of modem control pins: nCTS and nRTS. These modem control pins provide full
hardware flow control. Other modem control pins can be implemented via GPIOs. The HWUART
baud rate is programmable as fast as 921.6 Kbps.
The HWUART’s pins are multiplexed with the PCMCIA control pins. Because of this, these
HWUART pins operate at the same voltage as the memory bus. Also, since the PCMCIA pin
nPWE is used for variable-latency input/output (VLIO), while using these pins for the HWUART,
VLIO is unavailable. The HWUART pins are also available over the BTUART pins. When
operating over the BTUART pins, the HWUART pins operate at the I/O voltage.