Intel PXA26X - Manual (Page 27)

Intel® PXA26x Processor Family Developer’s Manual 1-3
Introduction
The 3.6864-MHz crystal drives a core phase locked loop (PLL) and a peripheral PLL. The PLLs
produce selected clock frequencies to run particular functional blocks.
The 32.768-KHz crystal provides an optional clock source that must be selected after a hard reset.
This clock drives the real time clock, power management controller, and interrupt controller. The
32.768-KHz crystal is on a separate power island to provide an active clock while the processor is
in sleep mode.
Power management controls the transition between the turbo/run, idle, and sleep operating modes.
1.2.3 Universal Serial Bus (USB) Client
The USB client module is based on the Universal Serial Bus Specification, Revision 1.1. It supports
up to sixteen endpoints and provides an internally generated 48-MHz clock. The USB device
controller provides FIFOs with direct memory access (DMA) to or from memory.
1.2.4 Direct Memory Access Controller (DMAC)
The DMAC provides sixteen prioritized channels to service transfer requests from internal
peripherals and up to two data transfer requests from external companion chips. The DMAC is
descriptor-based to allow command chaining and looping constructs.
The DMAC operates in flow-through mode when performing peripheral-to-memory, memory-to-
peripheral, and memory-to-memory transfers. The DMAC is compatible with peripherals that use
word, half-word, or byte data sizes.
1.2.5 Liquid Crystal Display (LCD) Controller
The LCD controller supports both passive (DSTN) and active (TFT) flat-panel displays with a
maximum recommended resolution of 640x480x16-bit per pixel for 32 bit SDRAM buses, or
320x240x16-bit per pixel for 16 bit SDRAM buses. An internal 256 entry palette expands 1, 2, 4,
or 8-bit encoded pixels. Non-encoded 16-bit pixels bypass the palette.
Two dedicated DMA channels allow the LCD Controller to support single- and dual-panel
displays. Passive monochrome mode supports up to 256 gray-scale levels and passive color mode
supports up to 64K colors. Active color mode supports up to 64K colors.
1.2.6 AC97 Controller
The AC97 controller supports AC97 Revision 2.0 CODECs. These CODECs operate at sample
rates up to 48 KHz. The controller provides independent 16-bit channels for stereo pulse code
modulation (PCM) in, stereo PCM out, modem in, modem out, and mono microphone in. Each
channel includes a FIFO that supports DMA access to memory.
1.2.7 Inter-Integrated Circuit Sound (I
2
S) Controller
The I
2
S controller provides a serial link to standard I
2
S CODECs for digital stereo sound. It
supports both the normal I
2
S and MSB-justified I
2
S formats, and provides four signals for
connection to an I
2
S CODEC. I
2
S controller signals are multiplexed with AC97 controller pins.
The controller includes FIFOs that support DMA access to memory.