Intel PXA26X - Manual (Page 272)

7-4 Intel® PXA26x Processor Family Developer’s Manual
Liquid Crystal Display Controller
7.1.2 Pin Descriptions
When the LCD controller is enabled, all of the LCD pins are outputs only. When the LCD
controller is disabled, its pins are available for general-purpose input/output (GPIO). Refer to
Section 4, “System Integration Unit” for details.
Table 7-1 describes the LCD controller’s pins. For more detailed information, see Section 7.3.5,
“Liquid Crystal Display Controller Pin Usage” . All of the LCD pins are outputs only.
7.2 Liquid Crystal Display Controller Operation
7.2.1 Enabling the Controller
If the LCD controller is being enabled for the first time after system reset or sleep reset, all of the
LCD registers must be programmed to:
• Configure the general purpose I/O (GPIO) pins for LCD controller functionality. See
Chapter 4, “System Integration Unit” for details.
• Write the frame descriptors and, if needed, the palette descriptor to memory.
Table 7-1. Pin Descriptions
Pin Definition
L_DD[7:0]
PIXEL DATA PINS [7:0]:
These data lines transmit either four or eight data values at a time to the LCD display. For
monochrome displays, each pin value represents a single pixel. For passive color, groupings of
three pin values represent one pixel (red, green, and blue subpixel data values). In single-panel
monochrome mode, L_DD<3:0> pins are used. For double-pixel data, single-panel
monochrome, dual-panel monochrome, single-panel color, and active color modes, L_DD[7:0]
are used.
L_DD[15:8]
PIXEL DATA PINS [15:8]:
When dual-panel color or TFT (active-color mode) operation is programmed, these data outputs
are also required to send pixel data to the screen.
L_PCLK
PIXEL CLOCK:
Used by the LCD display to clock the pixel data into the line shift register. In passive mode, the
pixel clock toggles only when valid data is available on the data pins. In active mode, the pixel
clock toggles continuously, and L_BIAS serves as an output to signal when data is valid on the
LCD’s data pins.
L_LCLK
LINE CLOCK:
Used by the LCD display to signal the end of a line of pixels. The display transfers the line data
from the shift register to the screen and increments the line pointer. In active mode, it is the
horizontal-synchronization signal.
L_FCLK
FRAME CLOCK:
Used by the LCD display to signal the start of a new frame of pixels. The display resets the line
pointer to the top of the screen. In active mode, it is the vertical-synchronization signal.
L_BIAS
AC BIAS:
Signal the LCD display to switch the polarity of the power supplies to the row and column
drivers of the screen to counteract DC offset. In active mode, it serves as the output enable to
signal when data is latched from the data pins using the pixel clock.