Table 14-11. sadr bit descriptions, 8 controller: register memory map, Table 14-11 – Intel PXA26X User Manual
Page 511: Figure 14-3
Intel® PXA26x Processor Family Developer’s Manual
14-15
Inter-Integrated Circuit Sound Controller
Figure 14-3. Transmit and Receive FIFO Accesses Through the SADR
14.6.8
Controller: Register Memory Map
All registers are word addressable (32 bits wide) and hence increment in units of 0x00004. All
I2SC registers are mapped in the address range of 0x4040-000 through 0x404F-FFFF, as shown in
Table 14-11. SADR Bit Descriptions
Physical Address
0x4040-0080
Serial Audio Data Register
I
2
S Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DTH
DTL
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:16
DTH
Right data sample
15:0
DTL
Left data sample
TxEntry0
TxEntry1
TxEntry2
TxEntry3
TxEntry15
31
Right
Left
16 15
0
RxEntry0
RxEntry1
RxEntry2
RxEntry3
RxEntry15
31
Right
Left
16 15
0
SADR Register
31
0
Processor/DMA
TxFIFO
Written
Processor/DMA
RxFIFO
Read
PCM Transmit FIFO
PCM Receive FIFO
Write
Read
Transmit Data
Receive Data