Intel PXA26X - Manual (Page 67)

Intel® PXA26x Processor Family Developer’s Manual 3-1
Clocks and Power Manager
3
The clocks and power manager for the Intel® PXA26x Processor Family controls the clock
frequency to each module and manages transitions between the different power manager operating
modes to optimize both computing performance and power consumption.
The PXA26x processor family clocks and power manager supports 400-MHz run mode, and
CKEN bits for the NSSP, ASSP, and HWUART. Also, it includes nine new GPIOs that must be
defined in the Power Manager Sleep State registers.
3.1 Clock Manager Introduction
The clocks and power manager provides fixed clocks for each peripheral unit. Many of the devices’
peripheral clocks can be disabled using the Clock Enable register (CKEN), or through bits in the
peripheral’s control registers. To minimize power consumption, turn off the clock to any unit that is
not being used. The clocks and power manager also provides the programmable-frequency clocks
for the LCD controller, memory controller, and CPU. These clocks are related to each other
because they originate from the same internal phase locked loop (PLL) clock source. To program
the PLL’s frequency, follow these steps (for information on the factors L, M, and N, see
Section 3.6.1, “Core Clock Configuration Register (CCCR)” ):
1. Determine the fastest synchronous memory requirement (SDRAM frequency).
2. If the SDRAM frequency is less than 99.5 MHz, the memory frequency must be twice the
SDRAM frequency and the SDRAM clock ratio in the memory controller must be set to two.
If the SDRAM frequency is 99.5 MHz, the memory frequency is equal to the SDRAM
frequency.
3. Round the memory frequency down to the nearest value of 99.5 MHz (L = 0x1B), 118.0 MHz
(L = 0x20), 132.7 MHz (L = 0x24), 147.5 MHz (L = 0x28), or 165.9 MHz (L = 0x2D), and
program the value of L in the Core Clock Configuration Register (CCCR). This frequency (or
half, if the SDRAM clock ratio is 2) is the external synchronous memory frequency.
4. Determine the required core frequency for normal (run mode) operation. Use this mode during
normal processing, when the application must make occasional fetches to external memory.
The possible values are one, two, or four times the memory frequency. Program this value (M)
in the Core Clock Configuration Register.
5. Determine the required core frequency for turbo mode operation. This mode is generally used
when the application runs entirely from the caches, because any fetches to external memory
slow the core’s performance. This value is a multiple (1.0, 1.5, 2.0, or 3.0) of the run mode
frequency. Program the value (N) in the Core Clock Configuration Register.
6. Configure the LCD controller and memory controller for the new memory frequency and enter
the frequency change sequence (described in Section 3.4.8, “Frequency Change Sequence” ).
Note: Not all frequency combinations are valid. See Section 3.3.3, “Core Phase Locked Loop” for valid
combinations.