Yaskawa MP2300S Basic Module - Manual (Page 294)

7.3 Operation
7.3.3 Calculation of Slave CPU Synchronous Delay Time
7-16
7.3.3 Calculation of Slave CPU Synchronous Delay Time
In a slave CPU synchronous arrangement, a command from the master is processed as in the following flow, and trans-
mitted to the slave side.
Here, the time between c and f is constant.
This delay time is referred to as “Slave CPU Synchronous Delay Time” and is calculated as follows:
[Setting Example]
c
Execute master side application
Update output data
↓
d
SVB module processing Slave CPU synchronous delay time
↓
e
MECHATROLINK transmission
↓
f
Execute slave side application
Retrieve input data
Slave CPU synchronous delay time = Master H scan cycle × 2 + MECHATROLINK cycle
Master side H scan setting: 4 ms
MECHATROLINK communication cycle setting: 1 ms
↓
Slave CPU synchronous delay time = 4 ms × 2 + 1 ms
= 9 ms