Slave cpu synchronous function, Slave master master, 01 slave – Yaskawa MP2300S Basic Module User Manual
Page 307
7.4 Precautions
7.4.2 Effect of Error on Slave CPU Synchronous Operation
7-29
Slave CPU Synchronous Function
When the MP2300S with a built-in SVB works as a slave and the SVB-01 in an optional slot works
as a master, never connect them so that they form a loop, as shown in the following figure.
7.4.2 Effect of Error on Slave CPU Synchronous Operation
When an error occurs in a slave CPU synchronization, the slave side behavior reacts as follows:
Slave
Master
Master
SVB-01
TX
ERR
RUN
SPD
SIZE
M/S
ON
OFF
10
1
M-I/II
CN1
CN2
MP
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01
Slave
Action
State
The master side power is turned OFF
Continues to work in slave CPU asynchronous state.
An input error may occur, but other scan operations are not affected.
MECHATROLINK communication ca-
ble is disconnected
Continues to work in slave CPU asynchronous state.
An input error may occur, but other scan operations are not affected.
MP2300S assignment is deleted in
the master assignment
Continues to work in slave CPU asynchronous state.
An input error may occur, but other scan operations are not affected.
MECHATROLINK definition is saved
in the master side
Enters slave CPU asynchronous state once.
When a control bit SLVSC=OFF, the master side will recover and communication
will be resumed, and then enters slave CPU synchronous state again.
A transmission error occurs
If only a received data error occurs, it may not affect slave CPU synchronization.
However, as the input data is not updated, when you are checking the state using a
user application, a scan counter error may be detected according to the scan cycle and
communication cycle settings.
When an error (transmission cycle disturbance) of the MECHATROLINK communi-
cation itself occurs, it may affect slave CPU synchronization. In some cases, the
MP2300S H-scan process may be disturbed.
RUN/STOP of the master side CPU
CPU RUN/STOP does not affect slave CPU synchronization.
RUN/STOP of the slave side CPU
CPU RUN/STOP does not affect slave CPU synchronization.
Master side H scan setting is changed
Enters slave CPU asynchronous state once. When the changed H scan setting meets
the execution requirement of slave CPU synchronization and control bit
SLVSC=OFF, enters slave CPU synchronous state again.
Slave side H scan setting is changed
Enters slave CPU asynchronous state once. When the changed H scan setting meets
the execution requirement of slave CPU synchronization and control bit
SLVSC=OFF, enters slave CPU synchronous state again.