Motorola MPC8260 - Manual (Page 1003)

Overview
PowerPC Processor Core
Memory Map
System Interface Unit (SIU)
Reset
External Signals
60x Signals
The 60x Bus
Clocks and Power Control
Memory Controller
Secondary (L2) Cache Support
IEEE 1149.1 Test Access Port
Communications Processor Module Overview
Serial Interface with Time-Slot Assigner
CPM Multiplexing
Baud-Rate Generators (BRGs)
Timers
SDMA Channels and IDMA Emulation
Serial Communications Controllers (SCCs)
SCC UART Mode
SCC HDLC Mode
SCC BISYNC Mode
SCC Transparent Mode
SCC Ethernet Mode
SCC AppleTalk Mode
Serial Management Controllers (SMCs)
Multi-Channel Controllers (MCCs)
Fast Communications Controllers
ATM Controller
Fast Ethernet Controller
FCC HDLC Controller
FCC Transparent Controller
Serial Peripheral Interface (SPI)
I
2
C Controller
Parallel I/O Ports
Register Quick Reference Guide
Glossary
Index
3
4
5
6
7
8
9
10
1
GLO
IND
12
13
14
15
16
17
18
19
11
20
22
23
24
25
26
27
28
29
21
30
32
33
34
31
35
2
A