Motorola MPC8260 - Manual (Page 354)

10-78 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Figure 10-65. UPM Read Access Data Sampling
10.6.4.4 Signals Negation
When the LAST bit is read in a RAM word, the current UPM pattern terminates. On the
next cycle all the UPM signals are negated unconditionally (driven to logic Ф1Х).
This negation will not occur only if there is a back-to-back UPM request pending. In this
case the signals value on the cycle following the LAST bit, will be taken from the Þrst line
of the pending UPM routine.
10.6.4.5 The Wait Mechanism
The WAEN bit in the RAM array word, shown in Table 10-35, can be used to enable the
UPM wait mechanism in selected UPM RAM words.
If the UPM reads a RAM word with the WAEN bit set, the external UPWAIT signal is
sampled and synchronized by the memory controller and the current request is frozen. The
UPWAIT signal is sampled at the rising edge of CLKIN. If UPWAIT is asserted and
WAEN = 1 in the current UPM word, the UPM is frozen until UPWAIT is negated. The
value of the external pins driven by the UPM remains as indicated in the previous word read
by the UPM. When UPWAIT is negated, the UPM continues its normal functions. Note that
during the WAIT cycles, the UPM negates PSDVAL.
Figure 10-66 shows how the WAEN bit in the word read by the UPM and the UPWAIT
signal are used to hold the UPM in a particular state until UPWAIT is negated. As the
example in Figure 10-66 shows, the CSx and GPL1 states (C12 and F) and the WAEN value
(C) are frozen until UPWAIT is recognized as deasserted. WAEN is typically set before the
line that contain UTA = 1.
To internal
data bus
CLKIN
UPMx selected to handle the transfer
AND
(GPL4xDIS = 1) and RD/WR and DLT2x
Data Bus
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