Motorola MPC8260 - Manual (Page 76)

1-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
The MPC603e core has an internal common on-chip (COP) debug processor. This
processor allows access to internal scan chains for debugging purposes. It is also used as a
serial connection to the core for emulator support.
The MPC603e core performance for the SPEC 95 benchmark for integer operations ranges
between 4.4 and 5.1 at 200 MHz. In Dhrystone 2.1 MIPS, the MPC603e is 280 MIPS at
200 MHz (compared to 86 MIPS of the MPC860 at 66 MHz).
The MPC603e core can be disabled. In this mode, the MPC8260 functions as a slave
peripheral to an external core or to another MPC8260 device with its core enabled.
1.2.2 System Interface Unit (SIU)
The SIU consists of the following:
¥ A 60x-compatible parallel system bus conÞgurable to 64-bit data width. The
MPC8260 supports 64-, 32-, 16-, and 8-bit port sizes. The MPC8260 internal arbiter
arbitrates between internal components that can access the bus (system core, CPM,
and one external master). This arbiter can be disabled, and an external arbiter can be
used if necessary.
¥ A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is used
to enhance the operation of the very high-speed communication controllers. Without
requiring extensive manipulation by the core, the bus can be used to store connection
tables for ATM or buffer descriptors (BDs) for the communication channels or raw
data that is transmitted between channels. The local bus is synchronous to the 60x
bus and runs at the same frequency.
¥ Memory controller supporting 12 memory banks that can be allocated for either the
system or the local bus. The memory controller is an enhanced version of the
MPC860 memory controller. It supports three user-programmable machines.
Besides all MPC860 features, the memory controller also supports SDRAM with
page mode and address data pipeline.
¥ Supports JTAG controller IEEE 1149.1 test access port (TAP).
¥ A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt
timer, and other system functions useful in embedded applications.
¥ Glueless interface to L2 cache (MPC2605) and 4-/16-K-entry CAM (MCM69C232/
MCM69C432).
1.2.3 Communications Processor Module (CPM)
The CPM contains features that allow the MPC8260 to excel in a variety of applications
targeted mainly for networking and telecommunication markets.
The CPM is a superset of the MPC860 PowerQUICC CPM, with enhancements on the CP
performance and additional hardware and microcode routines that support high bit rate
protocols like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100-Mbps full-
duplex).