Motorola MPC8260 - Manual (Page 373)

MOTOROLA Chapter 10. Memory Controller 10-97
Part III. The Hardware Interface
Figure 10-81. Burst Write Access to EDO DRAM
cst1 0 0 0 0 0 0 0 0 0 0 Bit 0
cst2 0 0 0 0 0 0 0 0 0 0 Bit 1
cst3 0 0 0 0 0 0 0 0 0 0 Bit 2
cst4 0 0 0 0 0 0 0 0 0 1 Bit 3
bst1 1 1 0 0 1 0 1 0 1 0 Bit 4
bst2 1 1 0 0 0 0 0 1 0 1 Bit 5
bst3 1 0 0 0 0 1 0 1 0 1 Bit 6
bst4 1 0 0 1 0 1 0 1 0 1 Bit 7
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t1 1 1 1 1 1 1 1 1 1 1 Bit 12
g1t3 1 1 1 1 1 1 1 1 1 1 Bit 13
g2t1 Bit 14
g2t3 Bit 15
g3t1 Bit 16
g3t3 Bit 17
g4t1 Bit 18
g4t3 Bit 19
g5t1 Bit 20
g5t3 Bit 21
redo[0] Bit 22
redo[1] Bit 23
loop 0 0 0 0 0 0 0 0 0 0 Bit 24
exen 0 0 0 1 0 1 0 1 0 0 Bit 25
amx0 1 0 0 0 0 0 0 0 0 0 Bit 26
amx1 0 0 0 0 0 0 0 0 0 0 Bit 27
na 0 0 0 1 0 1 0 1 0 0 Bit 28
uta 0 0 1 0 0 1 0 1 0 1 Bit 29
todt 0 0 0 0 0 0 0 0 0 1 Bit 30
last 0 0 0 0 0 0 0 0 0 1 Bit 31
WBS WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 WBS+9
CLKIN
A
RD/WR
D
PSDVAL
CS1
BS
Row Column 1
(CAS)
(RAS)
GPL1
(OE)
Column 2 Column 3 Column 4