Motorola MPC8260 - Manual (Page 767)

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-9
Part IV. Communications Processor Module
Figure 28-3. FCC Memory Structure
The format of transmit and receive BDs, shown in Figure 28-4, is the same for every FCC
mode of operation except ATM mode; see Section 29.10.5, ÒATM Controller Buffer
Descriptors (BDs).Ó The Þrst 16 bits in each BD contain status and control information,
which differs for each protocol. The second 16 bits indicate the BD table length. The
remaining 32-bits contain the 32-bit address pointer to the actual buffer in memory.
For frame-based protocols, a message can reside in as many buffers as necessary (transmit
or receive). Each buffer has a maximum length of (64KÐ1) bytes. The CP does not assume
that all buffers of a single frame are currently linked to the BD table. It does assume,
however, that unlinked buffers are provided by the core soon enough to be sent or received.
Failure to do so causes an error condition being reported by the CP. An underrun error is
reported in the case of transmit; a busy error is reported in the case of receive. Because BDs
are prefetched, the receive BD table must always contain at least one empty BD to avoid a
busy error; therefore, RxBD tables must always have at least two BDs.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
offset + 0 Status and Control
offset + 2 Data Length
offset + 4 High-Order Data Buffer Pointer
offset + 6 Low-Order Data Buffer Pointer
Figure 28-4. Buffer Descriptor Format
Status and Control
Data Length
Buffer Pointer
FCCx TxBD Table Pointer
(TBASE)
FCCx RxBD Table Pointer
(RBASE)
FCCx RxBD
Table
FCCx TxBD
Table
Dual-Port RAM
Status and Control
Data Length
Buffer Pointer
Tx Buffer
External Memory
Rx Buffer Descriptors
Tx Buffer Descriptors
Rx Buffer