Motorola MPC8260 - Manual (Page 486)

14-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Figure 14-24. GCI Bus Signals
In addition to the 144-Kbps ISDN 2B+D channels, the GCI provides Þve channels for
maintenance and control functions:
¥ B1 is a 64-Kbps bearer channel
¥ B2 is a 64-Kbps bearer channel
¥ M is a 64-Kbps monitor channel
¥ D is a 16-Kbps signaling channel
¥ C/I is a 48-Kbps C/I channel (includes A and E bits)
The M channel is used to transfer data between layer 1 devices and the control unit (the
CPU); the C/I channel is used to control activation/deactivation procedures or to switch test
loops by the control unit. The M and C/I channels of the GCI bus should be routed to SMC1
or SMC2, which have modes to support the channel protocols. The MPC8260 can support
any channel of the GCI bus in the primary rate by modifying SIx RAM programming.
The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation
since it can access each bit of the GCI separately. The current-route RAM speciÞes which
bits are supported by the interface and which serial controller support them. The receiver
only receives the bits that are enabled by the SIx RAM and the transmitter only transmits
the bits that are enabled by the SIx RAM and does not drive L1TXDx. Otherwise, L1TXDx
is an open-drain output and should be pulled high externally.
The MPC8260 supports contention detection on the D channel of the SCIT bus. When the
MPC8260 has data to transmit on the D channel, it checks a SCIT bus bit that is marked
with a special route code (usually, bit 4 of C/I channel 2). The physical layer device
monitors the physical layer bus for activity on the D channel and indicates on this bit that
the channel is free. If a collision is detected on the D channel, the physical layer device sets
bit 4 of C/I channel 2 to logic high. The MPC8260 then aborts its transmission and
retransmits the frame when this bit is set again. This procedure is automatically handled for
the Þrst two buffers of a frame.
L1CLK
L1SYNC
L1RXD
L1TXD
B1 B2
B1 B2 M (Monitor) C/I A E
M (Monitor) C/I A E
(2X the data rate)
Notes: Clock is not to scale.
L1CLKO is not shown.
D2 D1
D1 D2