Motorola MPC8260 - Manual (Page 786)

29-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
generated and inserted into the cell. The MPC8260 supports synchronous residual time
stamp (SRTS) generation using external PLL. If this mode is enabled, the MPC8260 reads
the SRTS code from the external logic and inserts it into four outgoing cells. See
Section 29.15, ÒSRTS Generation and Clock Recovery Using External Logic.Ó
For the structured format, the transmitter reads 47 or 46 bytes from the external buffer and
inserts them into the AAL1 user data Þeld. The CP generates the AAL1 PDU header and
inserts it into the cell. The header consists of the SN, SNP, and the structured pointer.
The MPC8260 supports partially Þlled cells conÞgured on a per-VC basis; only valid octets
are copied from the TxBD to the ATM cell. The rest of the cell is Þlled with padding octets.
29.2.1.3 AAL0 Transmitter Overview
No speciÞc adaptation layer is provided for AAL0. The ATM controller reads a whole cell
from an external buffer, which always contains exactly one AAL0 cell. The ATM controller
optionally generates CRC10 on the cell payload and places it at the end of the payload
(CRC10 Þeld). AAL0 mode can be used to send OAM cells or AAL3/4 raw cells.
29.2.1.4 Transmit External Rate and Internal Rate Modes
The ATM controller supports the following two rate modes:
¥ External rate modeÑThe total transmission rate is determined by the PHY
transmission rate. The FCC sends cells to keep the PHY FIFOs full; the FCC inserts
idle/unassign cells to maintain the transmission rate.
¥ Internal rate modeÑThe total transmission rate is determined by the FCC internal
rate timers. In this mode, the FCC does not insert idle/unassign cells. The internal
rate mechanism is supported for the Þrst four PHY devices (PHY address 00-03).
Each PHY has its own FTIRR, described in Section 29.13.4, ÒFCC Transmit Internal
Rate Registers (FTIRRx).Ó The FTIRR includes the initial value of the internal rate
timer. A cell transmit request is sent when an internal rate timer expires. When using
internal rate mode, the user assigns one of the baud-rate generators (BRGs) to clock
the four internal rate timers.
29.2.2 Receiver Overview
Before the receiver is enabled, the host must initialize the MPC8260 and create the receive
data structure described in Section 29.10, ÒATM Memory Structure.Ó The host arranges a
BD table for each ATM channel. Buffers for each connection can be statically allocated
(that is, each BD in the BD table is associated with a Þxed buffer location) or in the case of
AAL5, can be fetched by the CP from a global free buffer pool. See Section 29.10.5, ÒATM
Controller Buffer Descriptors (BDs).Ó
The receiver ATM cell size is 53-65 bytes. The cell includes: 4 bytes ATM cell header, 1
byte HEC, which is ignored, and 48 bytes payload. User-deÞned cells (UDC mode) include
an extra header of 1Ð12 bytes with an optional HEC octet. Cell transfers use the UTOPIA
level II, cell-level handshake.