Motorola MPC8260 - Manual (Page 214)

6-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Note that CPM port multiplexing is described in the Chapter 35, ÒParallel I/O Ports.Ó
MODCK2
AP[2]
TC[1]
BNKSEL[1]
MODCK2ÑClock mode input. DeÞnes the operating mode of internal clock circuits.
Address parity 2Ñ(Input/output)The 60x master that drives the address bus, drives also the
address parity signals. The value driven on address parity 2 pin should give odd parity (odd number
of 1s) on the group of signals that includes address parity 2 and A[16Ð23].
Transfer code 1ÑThe transfer code output pins supply information that can be useful for debug
purposes for each of the MPC8260Õs initiated bus transactions.
Bank select 1ÑThe bank select outputs are used for selecting SDRAM bank when the MPC8260 is
in 60x-compatible bus mode.
MODCK3
AP[3]
TC[2]
BNKSEL[2]
MODCK3ÑClock mode input. DeÞnes the operating mode of internal clock circuits.
Address parity 3Ñ(Input/output)The 60x master that drives the address bus, drives also the
address parity signals. The value driven on address parity 3 pin should give odd parity (odd number
of 1s) on the group of signals that includes address parity 3 and A[24Ñ31].
Transfer code 2ÑThe transfer code output pins supply information that can be useful for debug
purposes for each of the MPC8260Õs initiated bus transactions.
Bank select 2ÑThe bank select outputs are used for selecting SDRAM bank when the MPC8260 is
in 60x-compatible bus mode.
XFC External Þlter capacitanceÑInput connection for an external capacitor Þlter for PLL circuitry.
CLKIN Clock InÑPrimary clock input to MPC8260Õs PLL. In a PCI system, where the MPC8260 PCI
interface is operated from the PCI bus clock, CLKIN should be connected to the PCI bus clock. In
that case, the 60x bus clock is driven on CLKOUT.
PA[0Ð31] General-purpose I/O port A bits 0Ð31. See Chapter 35, ÒParallel I/O Ports.Ó
PB[4Ð31] General-purpose I/O port B bits 4Ð31. See Chapter 35, ÒParallel I/O Ports.Ó
PC[0Ð31] General-purpose I/O port C bits 0Ð31. See Chapter 35, ÒParallel I/O Ports.Ó
PD[4Ð31] General-purpose I/O port D bits 4Ð31. See Chapter 35, ÒParallel I/O Ports.Ó
Power Supply VDDÑThis is the power supply of the internal logic.
VDDHÑThis is the power supply of the I/O Buffers.
VCCSYNÑThis is the power supply of the PLL circuitry.
GNDSYNÑThis is a special ground of the PLL circuitry.
VCCSYN1ÑThis is the power supply of the coreÕs PLL circuitry.
Table 6-1. External Signals (Continued)
Signal Description