Motorola MPC8260 - Manual (Page 431)

MOTOROLA Chapter 13. Communications Processor Module Overview 13-1
Chapter 13
Communications Processor Module
Overview
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The MPC8260Õs communications processor module (CPM) is a superset of the MPC860
PowerQUICC CPM, with enhancements in performance and the addition of hardware and
microcode routines for supporting high bit-rate protocols like ATM and Fast Ethernet. The
support for multiple HDLC channels is enhanced to support up to 256 HDLC channels.
13.1 Features
The CPM includes various blocks to provide the system with an efÞcient way to handle data
communication tasks. The following is a list of the CPMÕs important features.
¥ Communications processor (CP)
Ñ One instruction per clock
Ñ Executes code from internal ROM or dual-port RAM
Ñ 32-bit RISC architecture
Ñ Tuned for communication environments: instruction set supports CRC
computation and bit manipulation.
Ñ Internal timer
Ñ Interfaces with the PowerPCª embedded core processor through a 24-Kbyte
dual-port RAM and virtual DMA channels for each peripheral controller
Ñ Handles serial protocols and virtual DMA.
¥ Three full-duplex fast serial communications controllers (FCCs) support the
following protocols:
Ñ ATM protocol through UTOPIA interface (FCC1 and FCC2 only)
Ñ IEEE802.3/Fast Ethernet
Ñ HDLC
Ñ Totally transparent operation
¥ Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/
transparent channels at 64 Kbps each, multiplexed on up to eight TDM interfaces