Motorola MPC8260 - Manual (Page 536)

18-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
18.5.3 Controlling 60x Bus Bandwidth
STS, DTS, and SS_MAX can be used to control the 60x bus bandwidth occupied by the
IDMA channel. In every mode except ßy-by mode, at least one transfer size parameter
(STS/DTS) must be initialized to the SS_MAX value. For memory-to-memory transfers,
the other transfer size parameter can be initialized to a smaller value used to control the 60x
bus bandwidth. For example, if the transfer size is N*32 bytes, each time the DMA
controller wins arbitration, it transfers N bursts before releasing the bus. When SS_MAX
bytes have been transferred, the controller reverts to single transactions (double-word,
word, half-word, or byte).
Memory-to-memory transfer sizes must evenly divide into SS_MAX and also be a multiple
of 32 (for bursting); see Table 18-7.
The size of the IDMA transfer buffer in the dual-port RAM should be determined by the
largest transfer (usually SS_MAX + 32 bytes) needed by one of the buses, while the other
transfer size can be programmed to control the bandwidth of the other bus.
Summarizing the above, a larger DMA transfer size provides for greater microcode
efÞciency and lower DMA bus latency, because the DMA controller does not release the
60x bus until the transfer is completed. If the DMA priority on the 60x bus is high, however,
other 60x masters may experience a high bus latency. Conversely, if the transfer size is
small, the DMA requests the 60x bus more often, DMA latency increases and microcode
efÞciency decreases.
The IDMA transfer size parameters give high ßexibility, but it is recommended to check
overall system performance with different IDMA parameter settings for maximum
throughput.
Note that the memory priority parameter DCM[LP] should be considered when dealing
with bus bandwidth usage.
18.6 IDMA Priorities
Each IDMA channel can be programmed to have a higher or lower priority relative to the
serial controllers or to have the lowest overall priority when requesting service from the CP.
The IDMA priorities are programmed in RCCR[DRxQP]; see Section 13.3.6, ÒRISC
Controller ConÞguration Register (RCCR).Ó Take care to avoid overrun or underrun errors
in the serial controllers when selecting high priorities for IDMA.
Additional priority over all serial controllers can be selected by setting DCM[LP]; see
Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó
18.7 IDMA Interface Signals
Each IDMA has three dedicated handshake control signals for transfers involving an
external peripheral device: DMA request (DREQ[1Ð4]), DMA acknowledge (DACK[1Р4])