Motorola MPC8260 - Manual (Page 604)

20-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Figure 20-10. SCC UART Interrupt Event Example
SCCE bits are cleared by writing ones; writing zeros has no effect. Unmasked bits must be
cleared before the CPM clears an internal interrupt request. Figure 20-11 shows SCCE/
SCCM for UART operation.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ GLR GLT Ñ AB IDL GRA BRKE BRKS Ñ CCR BSY TX RX
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)
Figure 20-11. SCC UART Event Register (SCCE) and Mask Register (SCCM)
CD IDL RX CCR IDL RX IDL BRKS BRKE IDL CD
Break
Line Idle
10 Characters
RXD
CD
Characters
Received by UART
Time
Line Idle
TXD
RTS
Characters
Transmitted by UART
CTS
TX CTS CTS
Line Idle Line Idle
7 Characters
Notes:
UART SCCE
Events
1. The first RX event assumes Rx buffers are 6 bytes each.
2. The second IDL event occurs after an all-ones character is received.
3. The second RX event position is programmable based on the MAX_IDL value.
4. The BRKS event occurs after the first break character is received.
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.
Legend :
A receive control character defined not to be stored in the Rx buffer.
Notes :
UART SCCE
Events
1. TX event assumes all seven characters were put into a single buffer and TxBD[CR]=1.
2. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.