Motorola MPC8260 - Manual (Page 976)

35-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
4. Write the corresponding SIMR (mask register) bit with a 1 to allow interrupts to be
generated to the core.
5. The pin value can be read at any time using PDATC.
Note
After connecting CTS or CD to the SCC/FCC, the user must
also choose the normal operation mode in GSMR[DIAG] to
enable and disable SCC/FCC transmission and reception with
these pins.
The IDMA-DREQ lines in ports C can assert an external request to the CP instead of
asserting an interrupt to the core. Each line can be programmed to assert an interrupt request
upon a high-to-low change or any change as conÞgured in SIEXR.
Note
Do not program the IDMAx-DREQ pins to assert external
requests to the IDMA, unless the IDMA is used. Otherwise,
erratic operation occurs.