Index – Motorola MPC8260 User Manual
Page 997
MOTOROLA
Index Index-17
INDEX
transparent mode, 23-12
UART mode, 20-19
SCCE register
SCCM (SCC mask) register
BISYNC mode, 22-15
HDLC mode, 21-12
transparent mode, 23-12
UART mode, 20-19
SCCM register
SCCS (SCC status) register
BISYNC mode, 22-16
HDLC mode, 21-14
transparent mode, 23-13
UART mode, 20-21
SCIT programming, 14-33
SCPRR_H (CPM high interrupt priority register), 4-19
SCPRR_L (CPM low interrupt priority register), 4-20
SDMA channels
bus arbitration, 18-2
bus transfers, 18-2
LDTEA, 18-4
LDTEM, 18-4
overview, 18-1
PDTEA, 18-4
PDTEM, 18-4
programming model, 18-3
registers, 18-3
SDMR, 18-4
SDSR, 18-3
SDMR (SDMA mask register), 18-4
SDRAM interface, see SDRAM machine
SDSR (SDMA status register), 18-3
Serial communications controllers (SCCs)
AppleTalk mode
connecting to AppleTalk, 25-3
operating LocalTalk frame, 25-1
overview, 25-1, 25-1
programming example, 21-23, 25-4
programming the controller, 25-3
BISYNC mode
commands, 22-5
control character recognition, 22-6
error handling, 22-9
frame reception, 22-3
frame transmission, 22-2
frames, classes, 22-1
memory map, 22-4
overview, 22-1
parameter RAM, 22-3
programming example, 22-18
programming the controller, 22-17
receiving synchronization sequence, 22-9
RxBD, 22-12
sending synchronization sequence, 22-9
TxBD, 22-14
Ethernet mode
address recognition, 24-11
collision handling, 24-13
commands, 24-10
connecting to Ethernet, 24-4
error handling, 24-14
frame reception, 24-6
hash table algorithm, 24-13
loopback, 24-14
overview, 24-1
programming example, 24-23
programming the controller, 24-10
receive buffer, 24-17
transmit buffer, 24-19
HDLC mode
accessing the bus, 21-19
bus controller, 21-17
collision detection, 21-17, 21-20
commands, 21-5
delayed RTS mode, 21-21
error handling, 21-6
features list, 21-2
GSMR, HDLC bus protocol programming, 21-23
interrupts, 21-13
memory map, 21-4
multi-master bus configuration, 21-18
overview, 21-1
parameter RAM, 21-3
performance, increasing, 21-20
programming example, 21-15, 21-23
programming the controller, 21-5
PSMR, 21-7
RxBD, 21-8
single-master bus configuration, 21-19
TxBD, 21-11
using the TSA, 21-22
overview
buffer descriptors, 19-10
controlling SCC timing, 19-18
DPLL operation, 19-22
features, 19-2
initialization, 19-17
interrupt handling, 19-16
parameter RAM, 19-13
reconfiguration, 19-26
reset sequence, 19-27
switching protocols, 19-27
transparent mode
achieving synchronization, 23-3
commands, 23-7
DSR receiver SYNC pattern lengths, 23-3
end of frame detection, 23-6
error handling, 23-8