Motorola MPC8260 - Manual (Page 99)

MOTOROLA Chapter 2. PowerPC Processor Core 2-11
Part I. Overview
Although the MPC8260 does not support ßoating-point arithmetic instructions, the FPRs
are provided to support ßoating-point load and store instructions, which can be executed by
the LSU. For these instructions to execute, the FPRs must be enabled (MSR[FP] = 1);
otherwise, a ßoating-point unavailable exception is taken. It is recommended that the FPRs
be enabled only when there is a need to access the FPRs, for example, to handle ßash
memory updates. Otherwise, the processor should run in default mode, with FPRs disabled
(MSR[FP] = 0).
2.3.1.2 MPC8260-SpeciÞc Registers
The set of registers speciÞc to the MPC603e are also shown in Figure 2-2. Most of these
are described in the MPC603e UserÕs Manual and are implemented in the MPC8260 as
follows:
¥ MMU software table search registers: DMISS, DCMP, HASH1, HASH2, IMISS,
ICMP, and RPA. These registers facilitate the software required to search the page
tables in memory.
¥ IABR. This register facilitates the setting of instruction breakpoints.
The hardware implementation-dependent registers (HIDx) are implemented differently in
the MPC8260, and they are described in the following subsections.
2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0)
The processor coreÕs implementation of HID0 differs from the MPC603e UserÕs Manual as
follows:
¥ Bit 5, HID0[EICE], has been removed. There is no support for pipeline tracking.
¥ Bit 24, HID0[IFEM], instruction fetch enable M, has been added.
¥ Bit 28, HID0[ABE], address broadcast enable, has been added.
Figure 2-3 shows the MPC8260 implementation of HID0.
Figure 2-3. Hardware Implementation Register 0 (HID0)
0 1 2 3 4 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EBD EBA PAR NAP DPM NHR ICE DCE DCFI
EMCP DOZE SLEEP ILOCK
DLOCK
ICFI
FBIOB NOOPTI
С С С
IFEM
С С С
ABE