Motorola MPC8260 - Manual (Page 166)

4-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part II. ConÞguration and Reset
4.3.2.2 60x Bus Arbiter ConÞguration Register (PPC_ACR)
The 60x bus arbiter conÞguration register (PPC_ACR), shown in Figure 4-22, deÞnes the
arbiter modes and parked master on the 60x bus.
Table 4-10 describes PPC_ACR Þelds.
4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)
The 60x bus arbitration-level registers, shown in Figure 4-23 and Figure 4-24, deÞne
arbitration priority of MPC8260 bus masters. Priority Þeld 0 has highest-priority. For
information about MPC8260 bus master indexes, see the description of PPC_ACR[PRKM]
in Table 4-10.
Bit 0 1 2 3 4 5 6 7
Field Ñ DBGD EARB PRKM
Reset Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó
R/W R/W
Addr 0x10028
Figure 4-22. PPC_ACR
Table 4-10. PPC_ACR Field Descriptions
Bits Name Description
0Р1 С Reserved, should be cleared.
2 DBGD Data bus grant delay. SpeciÞes the minimum number of data tenure wait states for 60x bus master-
initiated data operations. This is the minimum delay between TS and DBG.
0 DBG is asserted with TS if the data bus is free.
1 DBG is asserted one cycle after TS if the data bus is not busy.
See Section 8.5.1, ÒData Bus Arbitration.Ó
3 EARB External arbitration.
0 Internal arbitration is performed. See Section 8.3.1, ÒArbitration Phase.Ó
1 External arbitration is assumed.
4Ð7 PRKM Parking master.
0000 CPM high request level
0001 CPM middle request level
0010 CPM low request level
0011 Reserved
0100 Reserved
0101 Reserved
0110 Internal core
0111 External master 1
1000 External master 2
1001 External master 3
Values 1010Ð1111 are reserved.