Motorola MPC8260 - Manual (Page 898)

30-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Table 30-10 describes Ethernet RxBD Þelds.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 E Ñ W I L F Ñ M BC MC LG NO SH CR OV CL
Offset + 2 Data Length
Offset + 4 Rx Data Buffer Pointer
Offset + 6
Figure 30-8. Fast Ethernet Receive Buffer (RxBD)
Table 30-10. RxBD Field Descriptions
Bits Name Description
0 E Empty
0 The buffer associated with this RxBD is full or reception terminated due to an error. The core can
examine or read to any Þelds of this RxBD. The CP does not use this BD as long as E = 0.
1 The associated buffer is empty. The RxBD and buffer are owned by the CP. Once E = 1, the core
should not write any Þelds of this RxBD.
1 Ñ Reserved, should be cleared.
2 W Wrap (Þnal BD in RxBD table)
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that
RBASE points to in the table. The number of RxBDs in this table is programmable and determined
only by the W bit.
The RxBD table must contain more than one BD in Ethernet mode.
3 I Interrupt
0 No interrupt is generated after this buffer is used.
1 FCCE[RXB] or FCCE[RXF] are set when this buffer is used by the Ethernet controller. These two
bits can cause interrupts if they are enabled.
4 L Last in frame. Set by the Ethernet controller when this buffer is the last in a frame. This implies the
end of the frame or a reception error, in which case one or more of the CL, OV, CR, SH, NO, and LG
bits are set. The Ethernet controller writes the number of frame octets to the data length Þeld.
0 Not the last buffer in a frame.
1 Last buffer in a frame.
5 F First in frame. Set by the Ethernet controller when this buffer is the Þrst in a frame.
0 Not the Þrst buffer in a frame.
1 First buffer in a frame.
6 Ñ Reserved, should be cleared.
7 M Miss. Set by the Ethernet controller for frames that are accepted in promiscuous mode, but are
ßagged as a miss by the internal address recognition. Thus, while using promiscuous mode, the user
uses the miss bit to determine quickly whether the frame is destined for this station. Valid only if
RxBD[I] is set.
0 The frame is received because the address is recognized.
1 The frame is received because of promiscuous mode (address is not recognized).
8 BC Broadcast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address
is the broadcast address.
9 MC Multicast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address
is a multicast address other than a broadcast address.