Motorola MPC8260 - Manual (Page 884)

30-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
0x72 PADDR1_H Hword The 48-bit individual address of this station. PADDR1_L is the lowest order half-
word, and PADDR1_H is the highest order half-word.
0x74 PADDR1_M Hword
0x76 PADDR1_L Hword
0x78 IBD_CNT Hword Internal BD counter
0x7A IBD_START Hword Internal BD start pointer
0x7C IBD_END Hword Internal BD end pointer
0x7E TX_LEN Hword Tx frame length counter
0x80 IBD_BASE 32
Bytes
Internal microcode usage
0xA0 IADDR_H Word Individual address Þlter high/low. Used in the hash table function of the individual
addressing mode. The user can write zeros to these values after reset and before the
Ethernet channel is enabled to disable all individual hash address recognition
functions. Issuing a
SET GROUP ADDRESS command enables the hash table. See
Section 30.13, ÒHash Table Algorithm.Ó
0xA4 IADDR_L Word
0xA8 MINFLR Hword Minimum frame length register (typically 64 decimal). If the Ethernet receiver detects
an incoming frame shorter than MINFLR, it discards that frame unless FPSMR[RSH]
(receive short frames) is set, in which case RxBD[SH] (frame too short) is set in the
last RxBD. The Ethernet transmitter pads frames that are too short (according to
TxBD[PAD] and the PAD value in the parameter RAM). PADs are added to make the
transmit frame MINFLR bytes.
0xAA TADDR_H Hword Allows addition of addresses to the individual and group hashing tables. After an
address is placed in TADDR, issue a SET GROUP ADDRESS command. TADDR_L is
the lowest-order half-word; TADDR_H is the highest.
A zero in the I/G bit indicates an individual address; 1 indicates a group address. 0xAC TADDR_M Hword
0xAE TADDR_L Hword
0xB0 PAD_PTR Hword Internal PAD pointer. This internal 32-byte aligned pointer points to a 32-byte buffer
Þlled with pad characters. The pads may be any value, but all the bytes should be the
same to assure padding with a speciÞc character. If a speciÞc padding character is
not needed, PAD_PTR should equal the internal temporary data pointer TIPTR; see
Section 28.7, ÒFCC Parameter RAM.Ó
0xB2 Ñ Hword Reserved, should be cleared.
0xB4 CF_RANGE Hword Control frame range. Internal usage
0xB6 MAX_B Hword Maximum BD byte count. Internal usage
0xB8 MAXD1 Hword Max DMA1 length register (typically 1520 decimal). Lets the user prevent system bus
writes after a frame exceeds a speciÞed size. The MAXD1 value is valid only if an
address match is detected. If the Ethernet controller detects an incoming Ethernet
frame larger than the user-deÞned value in MAXD1, the rest of the frame is
discarded. The Ethernet controller waits for the end of the frame (or until MFLR bytes
have been received) and reports the frame status and length (including the
discarded bytes) in the last RxBD. This value must be greater than 32.
Table 30-2. Ethernet-Specific Parameter RAM (Continued)
Offset 1 Name Width Description