Motorola MPC8260 - Manual (Page 689)

MOTOROLA Chapter 24. SCC Ethernet Mode 24-21
Part IV. Communications Processor Module
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer
Descriptors (BDs).Ó
24.20 SCC Ethernet Event Register (SCCE)/Mask
Register (SCCM)
The SCC event register (SCCE) is used as the Ethernet event register to generate interrupts
and report events recognized by the Ethernet channel. When an event is recognized, the
Ethernet controller sets the corresponding SCCE bit. Interrupts are enabled by setting, and
masked by clearing, the equivalent bits in the Ethernet mask register (SCCM). SCCE bits
are cleared by writing ones; writing zeros has no effect. All unmasked bits must be cleared
before the CPM clears the internal interrupt request.
Table 24-9 describes SCCE and SCCM Þelds.
9 RL Retransmission limit. Set when the transmitter fails (Retry Limit + 1) attempts to successfully transmit
a message because of repeated collisions on the medium. The Ethernet controller writes this bit after
it Þnishes attempting to send the buffer.
10Ð13 RC Retry count. Indicates the number of retries required before the frame was sent successfully. If RC =
0, the frame was sent correctly the Þrst time. If RC = 15 and RET_LIM = 15 in the parameter RAM, 15
retries were required. Because the counter saturates at 15, if RC = 15 and RET_LIM > 15, then 15 or
more retries were required. The controller writes this Þeld after it successfully sends the buffer.
14 UN Underrun. Set when the Ethernet controller encounters a transmitter underrun while sending the
buffer. The Ethernet controller writes UN after it Þnishes sending the buffer.
15 CSL Carrier sense lost. Set when carrier sense is lost during frame transmission. The Ethernet controller
writes CSL after it Þnishes sending the buffer.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ GRA Ñ TXE RXF BSY TXB RXB
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)
Figure 24-9. SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
Table 24-9. SCCE/SCCM Field Descriptions
Bits Name Description
0Р7 С Reserved, should be cleared.
8 GRA Graceful stop complete. Set as soon the transmitter Þnishes any frame that was in progress when a
GRACEFUL STOP TRANSMIT command was issued. It is set immediately if no frame was in progress.
Table 24-8. SCC Ethernet Transmit TxBD Status and Control
Field Descriptions (Continued)
Bits Name Description