Motorola MPC8260 - Manual (Page 146)

4-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part II. ConÞguration and Reset
¥ Two priority schemes for the SCCs: grouped, spread
¥ Programmable highest priority request
¥ Unique vector number for each interrupt source
4.2.1 Interrupt ConÞguration
Figure 4-8 shows the MPC8260 interrupt structure. The interrupt controller receives
interrupts from internal sources, such as the PIT or TMCNT, from the CPM, and from
external pins (port C parallel I/O pins).
Figure 4-8. MPC8260 Interrupt Structure
MCP
IRQ[0Ð7]
INT
OR
PowerPC
Core
Port C[0Ð15]
Timer1
Timer2
Timer3
Timer4
SCC3
SCC4
SMC1
SPI
I 2 C
SMC2
Software Watchdog Timer
IRQ0
Interrupt Controller
IDMA1
IDMA2
RISC Timers
Fall/
Level
SCC2
SCC1
MCC1
FCC3
FCC2
FCC1
PIT
TMCNT
Edge/
Fall
IDMA3
IDMA4
SDMA
MCC2
16
16