Motorola MPC8260 - Manual (Page 483)

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-29
Part IV. Communications Processor Module
of the D channel. If a collision is detected on the D channel, the physical layer device
negates L1GRx. The MPC8260 then stops sending and retransmits the frame when L1GRx
is reasserted. This procedure is handled automatically for the Þrst two buffers of a frame.
For the primary rate IDL, the MPC8260 supports up to four 8-bit channels in the frame,
determined by the SIx RAM programming. To support more channels, the user can route
more than one channel to each SCC and the SCC treats it as one high-speed stream and
store it in the same data buffers (appropriate only for transparent data). Additionally, the
MPC8260 can be used to assert strobes for support of additional external IDL channels.
The IDL interface supports the CCITT I.460 recommendation for data-rate adaptation since
it separately accesses each bit of the IDL bus. The current-route RAM speciÞes which bits
are supported by the IDL interface and by which serial controller. The receiver only
receives bits that are enabled by the receiver route RAM. Otherwise, the transmitter sends
only bits that are enabled by the transmitter route RAM and three-states L1TXDx.
14.6.2 IDL Interface Programming
To program an IDL interface, Þrst program SIxMR[GMx] to the IDL grant mode for that
channel. If the receive and transmit sections interface to the same IDL bus, set
SIxMR[CRTx] to internally connect the Rx clock and sync signals to the transmit section.
Then, program the SIx RAM used for the IDL channels to the preferred routing. See
Section 14.4.4, ÒSIx RAM Programming Example.Ó
DeÞne the IDL frame structure by programming SIxMR[xFSDx] to have a 1-bit delay from
frame sync to data, SIxMR[FEx] to sample on the falling edge, and SIxMR[CEx] to transmit
on the rising edge of the clock. Program the parallel I/O open-drain register so that L1TXDx
is three-stated when inactive; see Section 35.2.1, ÒPort Open-Drain Registers (PODRAÐ
PODRD).Ó To support the D channel, program the appropriate CMXSCR[GRx] bit, as
described in Section 15.4.5, ÒCMX SCC Clock Route Register (CMXSCR),Ó and program
the SIx RAM entry to route data to the chosen serial controller. The two deÞnitions of IDL,
8 or 10 bits, are implemented by simply modifying the SIx RAM programming. In both
cases, L1GRx is sampled with L1TSYNCx and transferred to the D-channel SCC as a grant
indication.