Cpm high interrupt priority register (scprr_h) -19, Siprr field descriptions -19 – Motorola MPC8260 User Manual
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MOTOROLA
Chapter 4. System Interface Unit (SIU)
4-19
Part II. ConÞguration and Reset
The SIPRR register bits are described in Table 4-5.
4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)
The CPM high interrupt priority register (SCPRR_H), shown in Figure 4-12, deÞne
priorities between the FCCs and MCCs.
Table 4-5. SIPRR Field Descriptions
Bits
Name
Description
0Ð3
XS1PÐXSIU1
Priority order. DeÞnes which PIT/TMCNT/IRQs asserts its request in the XSIU1 priority
position. The user should not program the same PIT/TMCNT/IRQs to more than one priority
position (1Ð8). These bits can be changed dynamically.
000 TMCNT asserts its request in the XSIU1 position.
001 PIT asserts its request in the XSIU1 position.
010 Reserved
011 IRQ1 asserts its request in the XSIU1 position.
100 IRQ2 asserts its request in the XSIU1 position.
101 IRQ3 asserts its request in the XSIU1 position.
110 IRQ4 asserts its request in the XSIU1 position.
111 IRQ5 asserts its request in the XSIU1 position.
4Ð12
XS2PÐ XS8P
Same as XS1P, but for XSIU2ÐXSIU8.
13Р15
С
Reserved, should be cleared.
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
XC1P
XC2P
XC3P
XC4P
С
С
Reset
000
001
010
011
0
000
R/W
R
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Addr
Bits
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
XC5P
XC6P
XC7P
XC8P
С
С
Reset
100
101
110
111
0
000
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Addr
0x10C16
Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H)