Motorola MPC8260 - Manual (Page 783)

29-3 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Ð Sequence number check
Ð Sequence number protection (CRC-3 and parity) check
Ñ Segmentation
Ð Segment PDU directly from external memory
Ð Partially Þlled cells support (conÞgurable on a per-VC basis)
Ð Sequence number generation
Ð Sequence number protection (CRC-3 and even parity) generation
Ñ Structured AAL1 cell format
Ð Automatic synchronization using the structured pointer during reassembly
Ð Structured pointer generation during segmentation
Ñ Unstructured AAL1 cell format
Ð Clock recovery using external SRTS (synchronous residual time stamp) logic
during reassembly
Ð SRTS generation using external logic during segmentation
¥ AAL0 format
Ñ Receive
Ð Whole cell is put in memory
Ð CRC10 pass/fail indication
Ñ Transmit
Ð Reads a whole cell from memory
Ð CRC10 insertion option
¥ Support for user-deÞned cells
Ñ Support cells up to 65 bytes
Ñ Extra header insert/load on a per-frame basis
Ñ Extra header size has byte resolution
Ñ Asymmetric cell size for send and receive
Ñ HEC octet insertion option
¥ PHY
Ñ UTOPIA level II supports 8/16 bits 25/50 MHz
Ð Supports UTOPIA master and slave modes
Ð Supports cell-level handshake
Ð Supports multiple-PHY polling mode
¥ ATM pace control (APC) unit
Ñ Peak cell rate pacing on a per-VC basis
Ñ Peak-and-sustain cell rate pacing using GCRA on a per-VC basis
Ñ Peak-and-minimum cell rate pacing on a per-VC basis
Ñ Up to eight priority levels
Ñ Fully managed by CP with no host intervention