Motorola MPC8260 - Manual (Page 856)

29-76 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
29.10.5.9 AAL1 TxBDs
Figure 29-51 shows the AAL1 TxBD.
Table 29-39 describes AAL1 TxBD Þelds.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0x00 R Ñ W I Ñ CM Ñ
Offset + 0x02 Data Length (DL)
Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR)
Offset + 0x06
Figure 29-51. AAL1 TxBD
Table 29-39. AAL1 TxBD Field Descriptions
Offset Bits Name Description
0x00 0 R Ready
0 The buffer associated with this BD is not ready for transmission. The user is free to
manipulate this BD or its associated buffer. The CP clears this bit after the buffer has
been sent or after an error condition is encountered.
1 The buffer prepared for transmission by the user has not been sent or is being sent.
No Þelds of this BD may be written by the user once R is set.
1 Ñ Reserved, should be cleared.
2 W Wrap (Þnal BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from
the Þrst BD in the table (the BD pointed to by the channelÕs TCT[TBD_BASE]). The
number of TxBDs in this table is determined only by the W bit. The current table
cannot exceed 64 Kbytes.
3 I Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt
threshold.
4Р5 С Reserved, should be cleared.
6 CM Continuous mode
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated
buffer to be retransmitted automatically when the CP next accesses this BD.
7Р11 С Reserved, should be cleared.
0x02 Ñ DL The number of octets the ATM controller should transmit from this BDÕs buffer. It is not
modiÞed by the CP. The value of DL should be greater than zero.
0x04 Ñ TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may
reside in either internal or external memory. This value is not modiÞed by the CP.