Motorola MPC8260 - Manual (Page 894)

30-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
30.18.1 FCC Ethernet Mode Register (FPSMR)
In Ethernet mode, the FCC protocol-speciÞc mode register, shown in Figure 30-5,
functions as the Ethernet mode register.
Table 30-8 describes FPSMR Þelds.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field HBC FC SBT LPB LCW FDE MON Ñ PRO FCE RSH Ñ
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11324 (FPSMR3)
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ CAM BRO Ñ CRC Ñ
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3)
Figure 30-5. FCC Ethernet Mode Registers (FPSMR)
Table 30-8. FPSMR Ethernet Field Descriptions
Bits Name Description
0 HBC Heartbeat checking
0 Heartbeat checking is not performed. Do not wait for a collision after transmission.
1 Wait 40 transmit serial clocks for a collision asserted by the transceiver after transmission.
TxBD[HB] is set if the heartbeat is not heard within 40 transmit serial clocks.
1 FC Force collision
0 Normal operation.
1 The controller forces a collision on transmission of every transmit frame. The MPC8260
should be conÞgured in loopback operation when using this feature, which allows the user to
test the MPC8260 collision logic. It causes the retry limit to be exceeded for each transmit
frame.
2 SBT Stop backoff timer
0 The backoff timer functions normally.
1 The backoff timer (for the random wait after a collision) is stopped whenever carrier sense is
active. In this method, the retransmission is less aggressive than the maximum allowed in the
IEEE 802.3 standard. The persistence (P_PER) feature in the parameter RAM can be used in
combination with the SBT bit (or in place of the SBT bit).
3 LPB Local protect bit
0 Receiver is blocked when transmitter sends (default).
1 Receiver is not blocked when transmitter sends. Must be set for full-duplex operation. For
loopback operation, GFMR[DIAG] must be programmed also; see Section 28.2, ÒGeneral
FCC Mode Registers (GFMRx).Ó
4 LCW Late collision window
0 A late collision is any collision that occurs at least 64 bytes from the preamble.
1 A late collision is any collision that occurs at least 56 bytes from the preamble.