Motorola MPC8260 - Manual (Page 674)

24-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
The Ethernet controller stores the Þrst 5 to 8 bytes of the transmit frame in dual-port RAM
so they need not be retrieved from system memory in case of a collision. This improves bus
usage and latency when the backoff timer output requires an immediate retransmission. If
a collision occurs during frame transmission, the controller returns to the Þrst buffer for a
retransmission. The only restriction is that the Þrst buffer must contain at least 9 bytes.
Note that if an Ethernet frame consists of multiple buffers, do not reuse the Þrst BD until
the CPM clears the R bit of the last BD.
When the end of the current BD is reached and TxBD[L] is set, the FCS bytes are appended
(if the TC bit is set in the TxBD), and TENA is negated. This notiÞes the EEST of the need
to generate the illegal Manchester encoding that marks the end of an Ethernet frame. After
CRC transmission, the Ethernet controller writes the frame status bits into the BD and
clears the R bit. When the end of the current BD is reached and the L bit is not set, only the
R bit is cleared.
In either mode, whether an interrupt is issued depends on how the I bit is set in the TxBD.
The Ethernet controller proceeds to the next TxBD. Transmission can be interrupted after
each frame, after each buffer, or after a speciÞc buffer is sent. The Ethernet controller can
pad characters to short frames. If TxBD[PAD] is set, the frame is padded up to the value of
the minimum frame length register (MINFLR).
To send expedited data before previously linked buffers or for error situations, the
GRACEFUL STOP TRANSMIT command can be used to rearrange transmit queue before the
CPM sends all the frames; the Ethernet controller stops immediately if no transmission is
in progress or it will keep sending until the current frame either Þnishes or terminates with
a collision. When the Ethernet controller receives a
RESTART TRANSMIT command, it
resumes transmission. The Ethernet controller sends bytes least-signiÞcant bit Þrst.
24.5 SCC Ethernet Channel Frame Reception
The Ethernet receiver handles address recognition and performs CRC, short frame,
maximum DMA transfer, and maximum frame length checking with almost no core
intervention. When the core enables the Ethernet receiver, it enters hunt mode as soon as
RENA is asserted while CLSN is negated. In hunt mode, as data is shifted into the receive
shift register one bit at a time, the register contents are compared to the contents of the
SYN1 Þeld in the data synchronization register (DSR). This compare function becomes
valid a certain number of clocks after the start of the frame (depending on PSMR[NIB]). If
the two are not equal, the next bit is shifted in and the comparison is repeated. If a double-
zero or double-one fault is detected between bits 14 to 21 from the Þrst received preamble
bit, the frame is rejected. If a double-zero fault is detected after 21 bits from the Þrst
received preamble bit and before detection of the start frame delimiter (SFD), the frame is
also rejected. When the incoming pattern is not rejected and matches the DSR, the SFD has
been detected; hunt mode is terminated and character assembly begins.
When the receiver detects the Þrst bytes of the frame, the Ethernet controller performs