Motorola MPC8260 - Manual (Page 561)

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-5
Part IV. Communications Processor Module
25 TFL Transmit FIFO length.
0 Normal operation. The transmit FIFO is 32 bytes.
1 The Tx FIFO is 1 byte. This option is used with character-oriented protocols, such as UART, to
ensure a minimum FIFO latency at the expense of performance.
26 RFW Rx FIFO width.
0 Receive FIFO is 32 bits wide for maximum performance; the Rx FIFO is 32 bytes. Data is not
normally written to receive buffers until at least 32 bits are received. This conÞguration is required
for HDLC-type protocols and Ethernet and is recommended for high-performance transparent
protocols.
1 Low-latency operation. The receive FIFO is 8 bits wide, reducing the Rx FIFO to a quarter its
normal size. This allows data to be written to the buffer as soon as a character is received, instead
of waiting to receive 32 bits. This conÞguration must be chosen for character-oriented protocols,
such as UART. It can also be used for low-performance, low-latency, transparent operation.
However, it must not be used with HDLC, HDLC Bus, AppleTalk, or Ethernet because it causes
erratic behavior.
27 TXSY Transmitter synchronized to the receiver. Intended for X.21 applications where the transmitted data
must begin an exact multiple of 8-bit periods after the received data arrives.
0 No synchronization between receiver and transmitter (default).
1 The transmit bit stream is synchronized to the receiver. Additionally, if RSYN = 1, transmission in
totally transparent mode does not occur until the receiver synchronizes with the bit stream and
CTS is asserted to the SCC. Assuming CTS is asserted, transmission begins 8 clocks after the
receiver starts receiving data.
28Ð29 SYNL Sync length (BISYNC and transparent mode only). See the data synchronization register (DSR)
deÞnition in Section 22.9, ÒSending and Receiving the Synchronization Sequence,Ó (BISYNC) and
Section 23.4.1.1, ÒIn-Line Synchronization Pattern,Ó (transparent).
00 An external sync (CD) is used instead of the sync pattern in the DSR.
01 4-bit sync. The receiver synchronizes on a 4-bit sync pattern stored in the DSR. This sync and
additional syncs can be stripped by programming the SCCÕs parameter RAM for character
recognition.
10 8-bit sync. Should be chosen along with the BISYNC protocol to implement mono-sync. The
receiver synchronizes on an 8-bit sync pattern in the DSR.
11 16-bit sync. Also called BISYNC. The receiver synchronizes on a 16-bit sync pattern stored in the
DSR.
30 RTSM RTS mode. Determines whether ßags or idles are to be sent. Can be changed on-the-ßy.
0 Send idles between frames as deÞned by the protocol and the TEND bit. RTS is negated between
frames (default).
1 Send ßags/syncs between frames according to the protocol. RTS is always asserted whenever the
SCC is enabled.
31 RSYN Receive synchronization timing (totally transparent mode only).
0 Normal operation.
1 If CDS = 1
, CD should be asserted on the second bit of the Rx frame rather than on the Þrst.
Table 19-1. GSMR_H Field Descriptions (Continued)
Bit Name Description