Motorola MPC8260 - Manual (Page 582)

19-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
19.3.7 Clock Glitch Detection
Clock glitches cause problems for many communications systems, and they may go
undetected by the system. Systems that supply an external clock to a serial channel are often
susceptible to glitches from noise, connecting or disconnecting the physical cable from the
application board, or excessive ringing on a clock line. A clock glitch occurs when more
than one edge occurs in a time period that violates the minimum high or low time
speciÞcation of the input clock.
The SCCs on the MPC8260 have a special circuit designed to detect glitches and alert the
system of a problem at the physical layer. The glitch-detect circuit is not a speciÞcation test;
if a circuit does not meet the SCCÕs input clocking speciÞcations, erroneous data may not
be detected or false glitch indications can occur. Regardless of whether the DPLL is used,
the received clock is passed through a noise Þlter that eliminates any noise spikes that affect
a single sample. This sampling is enabled using GSMR_H[GDE].
If a spike is detected, a maskable Rx or Tx glitched clock interrupt is generated in
SCCEx[GLR,GLT]. Although the receiver or transmitter can be reset or allowed to continue
operation, statistics on clock glitches should be kept for evaluation to help in debugging,
especially during prototype testing.
19.3.8 ReconÞguring the SCCs
The proper reconÞguration sequence must be followed for SCC parameters that cannot be
changed dynamically. For instance, the internal baud rate generators allow on-the-ßy
changes, but the DPLL-related GSMR does not. The steps in the following sections show
how to disable, reconÞgure and re-enable an SCC to ensure that buffers currently in use are
properly closed before reconÞguring the SCC and that subsequent data goes to or from new
buffers according to the new conÞguration.
Modifying parameter RAM does not require the SCC to be fully disabled. See the
parameter RAM description for when values can be changed. To disable all peripheral
controllers, set CPCR[RST] to reset the entire CPM.
19.3.8.1 General ReconÞguration Sequence for an SCC Transmitter
An SCC transmitter can be reconÞgured by following these general steps:
1. If the SCC is sending data, issue a STOP TRANSMIT command. Transmission should
stop smoothly. If the SCC is not transmitting (no TxBDs are ready or the GRACEFUL
STOP TRANSMIT command has been issued and completed) or the INIT TX
PARAMETERS command is issued, the STOP TRANSMIT command is not required.
2. Clear GSMR_L[ENT] to disable the SCC transmitter and put it in reset state.
3. Modify SCC Tx parameters or parameter RAM. To switch protocols or restore the
initial Tx parameters, issue an INIT TX PARAMETERS command.