Motorola MPC8260 - Manual (Page 543)

18-19 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
10 SINC Source increment address.
0 Source address pointer (S_PTR) is not incremented in the source read transaction. Should
be cleared for peripheral-to-memory transfers if the peripheral has a Þxed address.
1 CP increments the source address pointer (S_PTR) with the number of bytes transferred in
the source read transaction. Used for memory-to-memory and memory-to-peripheral
transfers.
In ßy-by mode, SINC controls the memory address increment and should equal DINC.
11 DINC Destination increment address.
0 Destination address pointer (D_PTR) is not changed in the destination write transaction.
Used for memory-to-peripheral transfers if the peripheral has a Þxed address.
1 CP increments the destination pointer (D_PTR) with the number of bytes transferred in the
destination write transaction. Used for memory-to-memory and memory-to-peripheral
transfers.
In ßy-by mode, DINC should equal SINC.
12 ERM External request mode.
0 The CP transfers continuously, as if an external level request is asserted, regardless of the
DREQ signal assertion. The CP stops the transfer when there are no more valid BDs or
after a
STOP _ IDMA command is issued. DONE assertion by a external device is ignored.
1 The CP responds to DREQ as conÞgured (edge/level) by performing single- or dual-address
transfers. The CP also responds to DONE assertions.
Note: Memory-to-memory transfers (S/D=00) with external request (ERM=1) is allowed, but
DONE assertion is not supported in this mode (DONE should be disabled).
13 DT DONE treatment:
0 After external DONE assertion, the IDMA ignores further DREQ assertions. The CP closes
the current BD and IDMA stops. START _ IDMA command should be issued before assertion of
another DREQ.
1 After external DONE assertion, the CP closes the current BD. The IDMA continues to the
next BD when DREQ is asserted.
14Ð15 S/D Source/destination is a peripheral device or memory. See Table 18-6.
00 Read from memory, write to memory.
10 Read from peripheral, write to memory.
01 Read from memory, write to peripheral.
11 Reserved
When a device is a peripheral:
¥
DACK is asserted during transfers to/from it.
¥ It may assert DONE to terminate all accesses to/from it.
¥ It can be operated in ßy-by modeÑrespond to DACK ignoring the address.
¥ It gets highest DMA priority on the bus arbiter and the lowest DMA latency available.
Table 18-5. DCM Field Descriptions (Continued)
Bits Name Description