Motorola MPC8260 - Manual (Page 566)

19-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
The CP can be conÞgured to begin processing a new frame/buffer without waiting the
normal polling time by setting TODR[TOD] after TxBD[R] is set. Because this feature
favors the speciÞed TxBD, it may affect servicing of other SCC FIFOs. Therefore,
transmitting on demand should only be used when a high-priority TxBD has been prepared
and enough time has passed since the last g transmission. Table 19-3 describes TODR
Þelds.
19.2 SCC Buffer Descriptors (BDs)
Data associated with each SCC channel is stored in buffers and each buffer is referenced by
a buffer descriptor (BD) that can reside anywhere in dual-port RAM. The total number of
8-byte BDs is limited only by the size of the dual-port RAM (128 BDs/1 Kbyte). These BDs
are shared among all serial controllersÑSCCs, SMCs, SPI, and I
2 C. The user deÞnes how
the BDs are allocated among the controllers.
Each 64-bit BD has the following structure:
¥ The half word at offset + 0x0 contains status and control bits that control and report
on the data transfer. These bits vary from protocol to protocol. The CPM updates the
status bits after the buffer is sent or received.
¥ The half word at offset + 0x2 (data length) holds the number of bytes sent or
received.
Ñ For an RxBD, this is the number of bytes the controller writes into the buffer. The
CPM writes the length after received data is placed into the associated buffer and
the buffer closed. In frame-based protocols (but not including SCC transparent
operation), this Þeld contains the total frame length, including CRC bytes. Also,
if a received frameÕs length, including CRC, is an exact multiple of MRBLR, the
last BD holds no actual data but does contain the total frame length.
Ñ For a TxBD, this is the number of bytes the controller should send from its buffer.
Normally, this value should be greater than zero. The CPM never modiÞes this
Þeld.
Table 19-3. TODR Field Descriptions
Bits Name Description
0 TOD Transmit on demand.
0 Normal operation.
1 The CP gives high priority to the current TxBD and begins sending the frame without waiting the
normal polling time to check the TxBDÕs R bit. TOD is cleared automatically after one serial clock, but
transmitting on demand continues until an unprepared (R = 0) BD is reached. TOD does not need to
be set again if new TxBDs are added to the BD table as long as older TxBDs are still being
processed. New TxBDs are processed in order. The Þrst bit of the frame is typically clocked out 5-6
bit times after TOD is set.
1Р15 С Reserved, should be cleared.