Motorola MPC8260 - Manual (Page 745)

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-15
Part IV. Communications Processor Module
27.8 MCC ConÞguration Registers (MCCFx)
The MCC conÞguration register (MCCF), shown in Figure 27-11, deÞnes the mapping of
the MCC channels to the TDM channels. MCC1 can be connected to SI1 and MCC2 can
be connected to SI2. For each MCCx-SIx pair, each of the four 32 channels subgroups can
be connected to one of the four TDM highways (TDMA, TDMB, TDMC, and TDMD).
Table 27-9 describes MCCF Þelds.
Table 27-10 describes group assignments.
10 TS Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data
buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4
(N is any number larger than 0).
11Ð12 RQN Receive queue number. SpeciÞes the receive interrupt queue number.
00 Queue number 0.
01 Queue number 1.
10 Queue number 2.
11 Queue number 3.
13Р15 С Reserved, must be cleared.
Bits 0 1 2 3 4 5 6 7
Field Group 1 Group 2 Group 3 Group 4
Reset 0000_0000
R/W R/W
Addr 0x11B38 (MCCF1), 0x11B58 (MCCF2)
Figure 27-11. SI MCC Configuration Register (MCCF)
Table 27-9. MCCF Field Descriptions
Bits Name Description
0Р1, 2Р3, 4Р5, 6Р7 GROUP x Group x of channels is used by TDM y as shown in Table 27-10.
00 Group x is used by TDM A.
01 Group x is used by TDM B.
10 Group x is used by TDM C.
11 Group x is used by TDM D.
Table 27-8. CHAMR Field DescriptionsÑTransparent Mode (Continued)
Bits Name Description