Motorola MPC8260 - Manual (Page 240)

8-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
transaction, it skips the bus request delay and assumes address bus mastership on the next
cycle. For this case, BR is not asserted and the access latency seen by the device is
shortened by one cycle.
The MPC8260 and external device bus devices qualify BG by sampling ARTRY in the
negated state prior to taking address bus mastership. The negation of ARTRY during the
address retry window (one cycle after the assertion of AACK) indicates that no address
retry is requested. If a device detects ARTRY asserted, it cannot accept a address bus grant
during the ARTRY cycle or the cycle following. A device that asserts ARTRY due to a
modiÞed cache block hit, for example, asserts its bus request during the cycle after the
assertion of ARTRY and assumes bus mastership for the cache block push when it is given
a bus grant.
The series of address transfers in Figure 8-4 shows the transfer protocol when the
MPC8260 is conÞgured in 60x-compatible bus mode. In this example, MPC8260 is initially
parked on the bus with BG INT-asserted (note that BG INT is an internal signal not seen by
the user at the pins), which lets it start an address bus tenure by asserting TS. During the
same clock cycle, the external masterÕs bus request is asserted to request access to the 60x
bus, thereby causing the negation of BG INT internally and the assertion of BG at the pin.
Following MPC8260Õs address tenure, the external master takes the bus and initiates its
address transaction. The on-chip arbiter samples BR during the clock cycle in which AACK
is asserted; if BR is not asserted (no pending request), it negates BG and asserts the parked
bus grant (BG_INT in this example).
The master can assert BR and receive a qualiÞed bus grant without subsequently using the
bus. It can negate (cancel) BR before accepting a qualiÞed bus grant. This can occur when
a replacement copyback transaction waiting to be run on the bus is killed by a snoop of
another bus master. This can also occur when the reservation set by a pending stwcx.
transaction is cancelled by a snoop of another master. In both cases, the pending transaction
by the processor is cancelled and BR is negated.