Motorola MPC8260 - Manual (Page 33)

MOTOROLA Illustrations xxxiii
ILLUSTRATIONS
Figure
Number
Title
Page
Number
1-1 MPC8260 Block Diagram ......................................................................................... 1-5
1-2 MPC8260 External Signals........................................................................................ 1-8
1-3 Remote Access Server Configuration...................................................................... 1-11
1-4 Regional Office Router Configuration .................................................................... 1-12
1-5 LAN-to-WAN Bridge Router Configuration........................................................... 1-13
1-6 Cellular Base Station Configuration ........................................................................ 1-14
1-7 Telecommunications Switch Controller Configuration........................................... 1-14
1-8 SONET Transmission Controller Configuration ..................................................... 1-15
1-9 Basic System Configuration .................................................................................... 1-16
1-10 High-Performance Communication......................................................................... 1-16
1-11 High-Performance System Microprocessor Configuration ..................................... 1-17
2-1 MPC8260 Integrated Processor Core Block Diagram............................................... 2-2
2-2 MPC8260 Programming ModelÑRegisters............................................................ 2-10
2-3 Hardware Implementation Register 0 (HID0) ......................................................... 2-11
2-4 Hardware Implementation Register 1 (HID1) ......................................................... 2-15
2-5 Hardware Implementation-Dependent Register 2 (HID2) ...................................... 2-15
2-6 Data Cache Organization ......................................................................................... 2-20
4-1 .SIU Block Diagram .................................................................................................. 4-1
4-2 System Configuration and Protection Logic.............................................................. 4-3
4-3 Timers Clock Generation........................................................................................... 4-4
4-4 TMCNT Block Diagram............................................................................................ 4-5
4-5 PIT Block Diagram.................................................................................................... 4-5
4-6 Software Watchdog Timer Service State Diagram.................................................... 4-6
4-7 Software Watchdog Timer Block Diagram ............................................................... 4-7
4-8 MPC8260 Interrupt Structure .................................................................................... 4-8
4-9 Interrupt Request Masking ...................................................................................... 4-14
4-10 SIU Interrupt Configuration Register (SICR).......................................................... 4-17
4-11 SIU Interrupt Priority Register (SIPRR).................................................................. 4-18
4-12 CPM High Interrupt Priority Register (SCPRR_H) ................................................ 4-19
4-13 CPM Low Interrupt Priority Register (SCPRR_L) ................................................. 4-20
4-14 SIPNR_H Fields ...................................................................................................... 4-21
4-15 SIPNR_L Fields....................................................................................................... 4-21
4-16 SIMR_H Register .................................................................................................... 4-22
4-17 SIMR_L Register..................................................................................................... 4-23
4-18 SIU Interrupt Vector Register (SIVEC) .................................................................. 4-23
4-19 Interrupt Table Handling Example .......................................................................... 4-24