Motorola MPC8260 - Manual (Page 299)

MOTOROLA Chapter 10. Memory Controller 10-23
Part III. The Hardware Interface
23 BL Burst length
0 SDRAM burst length is 4. Use this value if the device port size is 64 or 16
1 SDRAM burst length is 8. Use this value if the device port size is 32 or 8
24Ð25 LDOTOPRE Last data out to precharge. DeÞnes the earliest timing for PRECHARGE command after the last
data was read from the SDRAM. See Section 10.4.6.4, ÒLast Data Out to Precharge.Ó
00 0 clock cycles
01 -1 clock cycle
10 -2 clock cycles
11 Reserved
26Ð27 WRC Write recovery time. DeÞnes the earliest timing for PRECHARGE command after the last data was
written to the SDRAM. See Section 10.4.6.5, ÒLast Data In to PrechargeÑWrite Recovery.Ó
01 1 clock cycles
10 2 clock cycles
11 3 clock cycles
00 4 clock cycles
28 EAMUX External address multiplexing enable/disable.
0 No external address multiplexing. Fastest timing.
1 The memory controller asserts SDAMUX for an extra cycle before issuing an
ACTIVATE
command to the SDRAM. This is useful when external address multiplexing can cause a
delay on the address lines. Note that if this bit is set, ACTTORW should be a minimum of 2.
In 60x-compatible mode, external address multiplexing is placed on the address lines. If the
additional delay of the multiplexing endangers the device setup time, EAMUX should be set.
Setting this bit causes the memory controller to add another cycle for each address phase.
Note that EAMUX can also be set in any case of delays on the address lines, such as address
buffers. See Section 10.4.6.7, ÒExternal Address Multiplexing Signal.Ó
29 BUFCMD If external buffers are placed on the control lines going to both the SDRAM and address lines,
setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles,
instead of one. See Section 10.4.6.8, ÒExternal Address and Command Buffers (BUFCMD).Ó
0 Normal timing for the control lines
1 All control lines except CS are asserted for two cycles
In 60x-compatible mode, external buffers may be placed on the command strobes, except CS,
as well as the address lines. If the additional delay of the buffers endangers the device setup
time, BUFCMD should be set, which causes the memory controller to add a cycle for each
SDRAM command.
30Ð31 CL CAS latency. DeÞnes the timing for Þrst read data after SDRAM samples a column address.
See Section 10.4.6.3, ÒColumn Address to First Data OutÑCAS Latency.Ó
00 Reserved
01 1
10 2
11 3
Table 10-7. PSDMR Field Descriptions (Continued)
Bits Name Description