Motorola MPC8260 - Manual (Page 560)

19-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Table 19-1 describes GSMR_H Þelds.
Table 19-1. GSMR_H Field Descriptions
Bit Name Description
0Р14 С Reserved, should be cleared.
15 GDE Glitch detect enable. Determines whether the SCC searches for glitches on the external Rx and Tx
serial clock lines. Regardless of the GDE setting, a Schmitt trigger on the input lines is used to
reduce signal noise.
0 No glitch detection. Clear GDE if the external serial clock exceeds the limits of glitch detection logic
(6.25 MHz assuming a 25-MHz system clock), if an internal BRG supplies the SCC clock, or if
external clocks are used and glitch detection matters less than power consumption.
1 Glitches can be detected and reported as maskable interrupts in the SCC event register (SCCE).
16Ð17 TCRC Transparent CRC (valid for totally transparent channel only). Selects the frame checking provided on
transparent channels of the SCC (either the receiver, transmitter, or both, as deÞned by TTX and
TRX). Although this conÞguration selects a frame check type, the decision to send the frame check is
made in the TxBD. Thus, frame checks are not needed in transparent mode and frame check errors
generated on the receiver can be ignored.
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1).
01 CRC16 (BISYNC). (X16 + X15 + X2 + 1).
10 32-bit CCITT CRC (Ethernet and HDLC).
(X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1).
11 Reserved.
18 REVD Reverse data (valid for a totally transparent channel only)
0 Normal operation.
1 Reverses the bit order for totally transparent channels on this SCC (either the receiver, transmitter,
or both) and sends the msb of each byte Þrst. Section 22.11, ÒBISYNC Mode Register (PSMR),Ó
describes reversing bit order in a BISYNC protocol.
19Ð20 TRX,
TTX
Transparent receiver/transmitter. The receiver, transmitter, or both can use totally transparent
operation, regardless of GSMR_L[MODE]. For example, to conÞgure the transmitter as a UART and
the receiver for totally transparent operations, set MODE = 0b0100 (UART), TTX = 0, and TRX = 1.
0 Normal operation.
1 The channel uses totally transparent mode, regardless of the protocol chosen in GSMR_L[MODE].
For full-duplex totally transparent operation, set both TTX and TRX.
Note that an SCC cannot operate with half in Ethernet mode and half in transparent mode. That is, if
MODE = 0b1100 (Ethernet), erratic operation occurs unless TTX = TRX.
21, 22 CDP,
CTSP
CD/CTS pulse. If this SCC is used in the TSA and is programmed in transparent mode, set CTSP
and refer to Section 23.4.2, ÒSynchronization and the TSA,Ó for options on programming CDP.
0 Normal operation (envelope mode). CD/CTS should envelope the frame. Negating CD/CTS during
reception causes a CD/CTS lost error.
1 Pulse mode. Synchronization occurs when CD/CTS is asserted; further CD/CTS transitions do not
affect reception.
23, 24 CDS,
CTSS
CD/CTS sampling. Determine synchronization characteristics of CD and CTS. If the SCC is in
transparent mode and is used in the TSA, CDS and CTSS must be set. Also, CDS and CTSS must
be set for loopback testing in transparent mode.
0 CD/CTS is assumed to be asynchronous with data. It is internally synchronized by the SCC, then
data is received (CD) or sent (CTS) after several clock delays.
1 CD/CTS is assumed to be synchronous with data, which speeds up operation. CD or CTS must
transition while the Rx/Tx clock is low, at which time, the transfer begins. Useful for connecting
MPC8260 in transparent mode since the RTS of one MPC8260 can connect directly to the CD/
CTS of another.