Motorola MPC8260 - Manual (Page 293)

MOTOROLA Chapter 10. Memory Controller 10-17
Part III. The Hardware Interface
5Ð11 SDAM SDRAM address mask. Provides masking for corresponding bits in the associated BRx. By
masking address bits independently, SDRAM devices of different size address ranges can be
used. Any clear bit masks the corresponding address bit. Any set bit causes the corresponding
address bit to be compared with the address pins. Address mask bits can be set or cleared in any
order, allowing a resource to reside in more than one area of the address map. SDAM can be read
or written at any time.
0000000128 Mbyte
100000064 Mbyte
110000032 Mbyte
111000016 Mbyte
11110008 Mbyte
11111004 Mbyte
11111102 Mbyte
11111111 Mbyte
12Ð16 LSDAM Lower SDRAM address mask. The user should reset LSDAM to 0x0 to implements a minimum
size of 1 Mbyte when using SDRAM
SDRAM Page Information
17Ð18 BPD Banks per device. Sets the number of internal banks per SDRAM device.
00 2 internal banks per device
01 4 internal banks per device
10 8 internal banks per device (not valid for 128-Mbyte SDRAMs)
11 Reserved
Note that for 128-Mbyte SDRAMs, BPD must be 00 or 01.
19Ð21 ROWST Row start address bit. Sets the demultiplexed row start address bit. The value of ROWST depends
on SDMR[PBI].
For xSDMR[PBI] = 0:
0010 A7
0100 A8
0110 A9
1000 A10
1010 A11
1100 A12
1110 A13
Other values are reserved For xSDMR[PBI] = 1:
0000 A0
0001 A1
...
1100 A12
1101Ð1111 Reserved
22 Ñ Reserved
23Ð25 NUMR Number of row address lines. Sets the number of row address lines in the SDRAM device.
000 9 row address lines
001 10 row address lines
010 11 row address lines
011 12 row address lines
100 13 row address lines
101 14 row address lines
110 15 row address lines
111 16 row address lines
26 PMSEL Page mode select. Selects page mode for the SDRAM connected to the memory controller bank.
0 Back-to-back page mode (normal operation). Page is closed when the bus becomes idle.
1 Page is kept open until a page miss or refresh occurs.
Table 10-4. ORx Field Descriptions (SDRAM Mode) (Continued)
Bits Name Description