Motorola MPC8260 - Manual (Page 280)

10-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Ñ Write-protection capability
Ñ Control signal generation machine selection on a per-bank basis
Ñ Flexible chip-select assignment between the 60x bus and the local bus
Ñ Supports internal or external masters on the 60x bus
Ñ Data buffer controls activated on a per-bank basis
Ñ Atomic operation
Ñ Extensive external memory-controller/bus-slave support
Ñ ECC/parity byte-select
Ñ Data pipeline to reduce data setup time for synchronous devices
¥ Synchronous DRAM machine (60x or local bus)
Ñ Provides the control functions and signals for glueless connection to
JEDEC-compliant SDRAM devices
Ñ Back-to-back page mode for consecutive, back-to-back accesses
Ñ Supports 2-, 4- and 8-way bank interleaving
Ñ Supports SDRAM port size of 64-bit (60x only), 32-bit, 16-bit and 8-bit
Ñ Supports external address and/or command lines buffering
¥ General-purpose chip-select machine (GPCM)Ñ60x or local bus
Ñ Compatible with SRAM, EPROM, FEPROM, and peripherals
Ñ Global (boot) chip-select available at system reset
Ñ Boot chip-select support for 8-, 16-, 32-, and 64-bit devices
Ñ Minimum two clock accesses to external device
Ñ Eight byte write enable signals (WE)Ñfour on the local bus
Ñ Output enable signal (OE)
Ñ External access termination signal (GTA)
¥ Three UPMs
Ñ Each machine can be assigned to the 60x or local bus.
Ñ Programmable-array-based machine controls external signal timing with a
granularity of up to one quarter of an external bus clock period
Ñ User-speciÞed control-signal patterns run when an internal or external master
requests a single-beat or burst read or write access.
Ñ UPM refresh timer runs a user-speciÞed control signal pattern to support refresh
Ñ User-speciÞed control-signal patterns can be initiated by software