Motorola MPC8260 - Manual (Page 350)

10-74 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Additional information about some of the RAM word Þelds is provided in the following
sections.
10.6.4.1.1 Chip-Select Signals (CxTx)
If BRx[MS] of the accessed bank selects a UPM on the currently requested cycle the UPM
manipulates the CS signal for that bank with timing as speciÞed in the UPM RAM word.
The selected UPM affects only assertion and negation of the appropriate CS signal. The
state of the selected CSx signal of the corresponding bank depends on the value of each
CSTn bit.
Figure 10-63 and the timing diagrams in Figure 10-60 show how UPMs control CS signals.
29 UTA UPM transfer acknowledge. Indicates assertion of PSDVAL, sampled by the bus interface in the
current cycle.
0 PSDVAL is not asserted in the current cycle.
1 PSDVAL is asserted in the current cycle.
30 TODT Turn-on disable timer. The disable timer associated with each UPM allows a minimum time to be
guaranteed between two successive accesses to the same memory bank. This feature is critical
when DRAM requires a RAS precharge time. TODT, turns the timer on to prevent another UPM
access to the same bank until the timer expires.The disable timer period is determined in
MxMR[DSx]. The disable timer does not affect memory accesses to different banks.
0 The disable timer is turned off.
1 The disable timer for the current bank is activated preventing a new access to the same bank
(when controlled by the UPMs) until the disable timer expires. For example, precharge time.
Note: TODT must be set together with LAST. Otherwise it is ignored.
31 LAST Last. If this bit is set, it is the last RAM word in the program. When the LAST bit is read in a RAM
word, the current UPM pattern terminates and the highest priority pending UPM request (if any) is
serviced immediately in the external memory transactions. If the disable timer is activated and the
next access is top the same bank, the execution of the next UPM pattern is held off for the number of
clock cycles speciÞed in MxMR[DSx].
0 The UPM continues executing RAM words.
1 The service to the UPM request is done.
Table 10-35. RAM Word Bit Settings (Continued)
Bit Name Description