Motorola MPC8260 - Manual (Page 617)

MOTOROLA Chapter 21. SCC HDLC Mode 21-9
Part IV. Communications Processor Module
Table 21-7 describes HDLC RxBD status and control Þelds.
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer
Descriptors (BDs).Ó Because HDLC is a frame-based protocol, RxBD[Data Length] of the
Table 21-7. SCC HDLC RxBD Status and Control Field Descriptions
Bits Name Description
0 E Empty.
0 The buffer is full or reception stopped because of an error. The core can read or write to any Þelds of
this RxBD. The CP does not use this BD while E = 0.
1 The buffer is not full. The CP controls the BD and buffer. The core should not update the BD.
1 Ñ Reserved, should be cleared.
2 W Wrap (last BD in the RxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data using the BD pointed to
by RBASE. The number of BDs in this table are programmable and determined only by RxBD[W] and
overall space constraints of the dual-port RAM.
3 I Interrupt.
0 SCCE[RXB] is not set after this buffer is used; SCCE[RXF] is unaffected.
1 SCCE[RXB] or SCCE[RXF] is set when the SCC uses this buffer.
4 L Last buffer in frame.
0 Not the last buffer in frame.
1 Last buffer in frame. Indicates reception of a closing ßag or an error, in which case one or more of the
CD, OV, AB, and LG bits are set. The SCC writes the number of frame octets to the data length Þeld.
5 F First in frame.
0 Not the Þrst buffer in a frame.
1 First buffer in a frame.
6 CM Continuous mode. Note that RxBD[E] is cleared if an error occurs during reception, regardless of CM.
0 Normal operation.
1 RxBD[E] is not cleared by the CP after this BD is closed, allowing the associated buffer to be
overwritten next time the CP accesses it.
7 Ñ Reserved, should be cleared.
8 DE DPLL error. Set when a DPLL error occurs while this buffer is being received. DE is also set due to a
missing transition when using decoding modes in which a transition is required for every bit. Note that
when a DPLL error occurs, the frame closes and error checking halts.
9 Ñ Reserved, should be cleared.
10 LG Rx frame length violation. Set when a frame larger than the maximum deÞned for this channel is
recognized. Only the maximum-allowed number of bytes (MFLR) is written to the buffer. This event is
not reported until the buffer is closed, SCCE[RXF] is set, and the closing ßag is received. The total
number of bytes received between ßags is still written to the data length Þeld.
11 NO Rx nonoctet aligned frame. Set when a received frame contains a number of bits not divisible by eight.
12 AB Rx abort sequence. Set when at least seven consecutive ones are received during frame reception.
13 CR Rx CRC error. Set when a frame contains a CRC error. CRC bytes received are always written to the
Rx buffer.
14 OV Overrun. Set when a receiver overrun occurs during frame reception.
15 CD Carrier detect lost (NMSI mode only). Set when CD is negated during frame reception.